SPRSP93B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes (F29H85x and F29P58x)
    3. 5.3 Pin Attributes (F29P32x)
    4. 5.4 Signal Descriptions
      1. 5.4.1 Analog Signals
      2. 5.4.2 Digital Signals
      3. 5.4.3 Test, JTAG, and Reset
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Pin Multiplexing
      1. 5.6.1 GPIO Muxed Pins
    7. 5.7 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  F29H85x ESD Ratings – Commercial
    3. 6.3  F29H85x ESD Ratings – Automotive
    4. 6.4  F29P58x ESD Ratings – Commercial
    5. 6.5  F29P58x ESD Ratings – Automotive
    6. 6.6  F29P32x ESD Ratings – Automotive
    7. 6.7  Recommended Operating Conditions
    8. 6.8  Power Consumption Summary
      1. 6.8.1 System Current Consumption VREG Disable - External Supply
      2. 6.8.2 System Current Consumption VREG Enabled
      3. 6.8.3 Operating Mode Test Description
      4. 6.8.4 Reducing Current Consumption
        1. 6.8.4.1 Typical Current Reduction per Disabled Peripheral
    9. 6.9  Electrical Characteristics
    10. 6.10 Special Considerations for 5V Fail-Safe Pins
    11. 6.11 Thermal Resistance Characteristics for ZEX Package
    12. 6.12 Thermal Resistance Characteristics for PTS Package
    13. 6.13 Thermal Resistance Characteristics for RFS Package
    14. 6.14 Thermal Resistance Characteristics for PZS Package
    15. 6.15 Thermal Design Considerations
    16. 6.16 System
      1. 6.16.1  Power Management Module (PMM)
        1. 6.16.1.1 Introduction
        2. 6.16.1.2 Overview
          1. 6.16.1.2.1 Power Rail Monitors
            1. 6.16.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.16.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.16.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.16.1.2.2 External Supervisor Usage
          3. 6.16.1.2.3 Delay Blocks
          4. 6.16.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.16.1.2.5 VREGENZ
        3. 6.16.1.3 External Components
          1. 6.16.1.3.1 Decoupling Capacitors
            1. 6.16.1.3.1.1 VDDIO Decoupling
            2. 6.16.1.3.1.2 VDD Decoupling
        4. 6.16.1.4 Power Sequencing
          1. 6.16.1.4.1 Supply Pins Ganging
          2. 6.16.1.4.2 Signal Pins Power Sequence
          3. 6.16.1.4.3 Supply Pins Power Sequence
            1. 6.16.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.16.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.16.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.16.1.4.3.4 Supply Slew Rate
        5. 6.16.1.5 Power Management Module Electrical Data and Timing
          1. 6.16.1.5.1 Power Management Module Operating Conditions
          2. 6.16.1.5.2 Power Management Module Characteristics
      2. 6.16.2  Reset Timing
        1. 6.16.2.1 Reset Sources
        2. 6.16.2.2 Reset Electrical Data and Timing
          1. 6.16.2.2.1 Reset XRSn Timing Requirements
          2. 6.16.2.2.2 Reset XRSn Switching Characteristics
          3. 6.16.2.2.3 Reset Timing Diagrams
      3. 6.16.3  Clock Specifications
        1. 6.16.3.1 Clock Sources
        2. 6.16.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.16.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.16.3.2.1.1 Input Clock Frequency
            2. 6.16.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.16.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.16.3.2.1.4 X1 Timing Requirements
            5. 6.16.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.16.3.2.1.6 APLL Characteristics
            7. 6.16.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.16.3.2.1.8 Internal Clock Frequencies
        3. 6.16.3.3 Input Clocks
        4. 6.16.3.4 XTAL Oscillator
          1. 6.16.3.4.1 Introduction
          2. 6.16.3.4.2 Overview
            1. 6.16.3.4.2.1 Electrical Oscillator
              1. 6.16.3.4.2.1.1 Modes of Operation
                1. 6.16.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.16.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.16.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.16.3.4.2.2 Quartz Crystal
            3. 6.16.3.4.2.3 GPIO Modes of Operation
          3. 6.16.3.4.3 Functional Operation
            1. 6.16.3.4.3.1 ESR – Effective Series Resistance
            2. 6.16.3.4.3.2 Rneg – Negative Resistance
            3. 6.16.3.4.3.3 Start-up Time
            4. 6.16.3.4.3.4 DL – Drive Level
          4. 6.16.3.4.4 How to Choose a Crystal
          5. 6.16.3.4.5 Testing
          6. 6.16.3.4.6 Common Problems and Debug Tips
          7. 6.16.3.4.7 Crystal Oscillator Specifications
            1. 6.16.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.16.3.4.7.2 Crystal Oscillator Parameters
            3. 6.16.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.16.3.5 Internal Oscillators
          1. 6.16.3.5.1 INTOSC Characteristics
      4. 6.16.4  Flash Parameters
        1. 6.16.4.1 C29 Flash Parameters 
        2. 6.16.4.2 HSM Flash Parameters 
      5. 6.16.5  Memory Subsystem (MEMSS)
        1. 6.16.5.1 Introduction
        2. 6.16.5.2 Features
        3. 6.16.5.3 RAM Specifications
      6. 6.16.6  Debug/JTAG
        1. 6.16.6.1 JTAG Electrical Data and Timing
          1. 6.16.6.1.1 DEBUGSS Timing Requirements
          2. 6.16.6.1.2 DEBUGSS Switching Characteristics
          3. 6.16.6.1.3 JTAG Timing Diagram
          4. 6.16.6.1.4 SWD Timing Diagram
      7. 6.16.7  GPIO Electrical Data and Timing
        1. 6.16.7.1 GPIO – Output Timing
          1. 6.16.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.16.7.1.2 General-Purpose Output Timing Diagram
        2. 6.16.7.2 GPIO – Input Timing
          1. 6.16.7.2.1 General-Purpose Input Timing Requirements
          2. 6.16.7.2.2 Sampling Mode
        3. 6.16.7.3 Sampling Window Width for Input Signals
      8. 6.16.8  Real-Time Direct Memory Access (RTDMA)
        1. 6.16.8.1 Introduction
          1. 6.16.8.1.1 Features
          2. 6.16.8.1.2 Block Diagram
      9. 6.16.9  Low-Power Modes
        1. 6.16.9.1 Clock-Gating Low-Power Modes
        2. 6.16.9.2 Low-Power Mode Wake-up Timing
          1. 6.16.9.2.1 IDLE Mode Timing Requirements
          2. 6.16.9.2.2 IDLE Mode Switching Characteristics
          3. 6.16.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.16.9.2.4 STANDBY Mode Timing Requirements
          5. 6.16.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.16.9.2.6 STANDBY Entry and Exit Timing Diagram
      10. 6.16.10 External Memory Interface (EMIF)
        1. 6.16.10.1 Asynchronous Memory Support
        2. 6.16.10.2 Synchronous DRAM Support
        3. 6.16.10.3 EMIF Electrical Data and Timing
          1. 6.16.10.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.16.10.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.16.10.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.16.10.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.16.10.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.16.10.3.6 EMIF Asynchronous Memory Timing Diagrams
    17. 6.17 C29x Analog Peripherals
      1. 6.17.1 Analog Subsystem
        1. 6.17.1.1 Features
        2. 6.17.1.2 Block Diagram
        3. 6.17.1.3 Analog Pin Connections
      2. 6.17.2 Analog-to-Digital Converter (ADC)
        1. 6.17.2.1 ADC Configurability
          1. 6.17.2.1.1 Signal Mode
        2. 6.17.2.2 ADC Electrical Data and Timing
          1. 6.17.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.17.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.17.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.17.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.17.2.2.5  ADC Timing Requirements
          6. 6.17.2.2.6  ADC Characteristics 12-bit Single-Ended
          7. 6.17.2.2.7  ADC Characteristics 12-bit Differential
          8. 6.17.2.2.8  ADC Characteristics 16-bit Single-Ended
          9. 6.17.2.2.9  ADC Characteristics 16-bit Differential
          10. 6.17.2.2.10 ADC INL and DNL
          11. 6.17.2.2.11 ADC Performance Per Pin
          12. 6.17.2.2.12 ADC Input Models
          13. 6.17.2.2.13 ADC Timing Diagrams
      3. 6.17.3 Temperature Sensor
        1. 6.17.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.17.3.1.1 Temperature Sensor Characteristics
      4. 6.17.4 Comparator Subsystem (CMPSS)
        1. 6.17.4.1 CMPSS Connectivity Diagram
        2. 6.17.4.2 Block Diagram
        3. 6.17.4.3 CMPSS Electrical Data and Timing
          1. 6.17.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.17.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.17.4.3.3 CMPSS Illustrative Graphs
      5. 6.17.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.17.5.1 Buffered DAC Electrical Data and Timing
          1. 6.17.5.1.1 Buffered DAC Operating Conditions
          2. 6.17.5.1.2 Buffered DAC Electrical Characteristics
    18. 6.18 C29x Control Peripherals
      1. 6.18.1 Enhanced Capture (eCAP)
        1. 6.18.1.1 eCAP Block Diagram
        2. 6.18.1.2 eCAP Synchronization
        3. 6.18.1.3 eCAP Electrical Data and Timing
          1. 6.18.1.3.1 eCAP Timing Requirements
          2. 6.18.1.3.2 eCAP Switching Characteristics
      2. 6.18.2 High-Resolution Capture (HRCAP)
        1. 6.18.2.1 eCAP and HRCAP Block Diagram
        2. 6.18.2.2 HRCAP Electrical Data and Timing
          1. 6.18.2.2.1 HRCAP Switching Characteristics
          2. 6.18.2.2.2 HRCAP Figure and Graph
      3. 6.18.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.18.3.1 Control Peripherals Synchronization
        2. 6.18.3.2 ePWM Electrical Data and Timing
          1. 6.18.3.2.1 ePWM Timing Requirements
          2. 6.18.3.2.2 ePWM Switching Characteristics
          3. 6.18.3.2.3 Trip-Zone Input Timing
            1. 6.18.3.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      4. 6.18.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.18.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.18.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.18.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.18.5.1 HRPWM Electrical Data and Timing
          1. 6.18.5.1.1 High-Resolution PWM Characteristics
      6. 6.18.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.18.6.1 eQEP Electrical Data and Timing
          1. 6.18.6.1.1 eQEP Timing Requirements
          2. 6.18.6.1.2 eQEP Switching Characteristics
      7. 6.18.7 Sigma-Delta Filter Module (SDFM)
        1. 6.18.7.1 SDFM Electrical Data and Timing
          1. 6.18.7.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
          2. 6.18.7.1.2 SDFM Electrical Data and Timing (Using ASYNC)
            1. 6.18.7.1.2.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
            2. 6.18.7.1.2.2 SDFM Timing Requirements When Using Synchronous GPIO SYNC Option
          3. 6.18.7.1.3 SDFM Timing Diagram
    19. 6.19 C29x Communications Peripherals
      1. 6.19.1 Modular Controller Area Network (MCAN)
      2. 6.19.2 Fast Serial Interface (FSI)
        1. 6.19.2.1 FSI Transmitter
          1. 6.19.2.1.1 FSITX Electrical Data and Timing
            1. 6.19.2.1.1.1 FSITX Switching Characteristics
            2. 6.19.2.1.1.2 FSITX Timings
        2. 6.19.2.2 FSI Receiver
          1. 6.19.2.2.1 FSIRX Electrical Data and Timing
            1. 6.19.2.2.1.1 FSIRX Timing Requirements
            2. 6.19.2.2.1.2 FSIRX Switching Characteristics
            3. 6.19.2.2.1.3 FSIRX Timings
        3. 6.19.2.3 FSI SPI Compatibility Mode
          1. 6.19.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.19.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.19.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 6.19.3 Inter-Integrated Circuit (I2C)
        1. 6.19.3.1 I2C Electrical Data and Timing
          1. 6.19.3.1.1 I2C Timing Requirements
          2. 6.19.3.1.2 I2C Switching Characteristics
          3. 6.19.3.1.3 I2C Timing Diagram
      4. 6.19.4 Power Management Bus (PMBus) Interface
        1. 6.19.4.1 PMBus Electrical Data and Timing
          1. 6.19.4.1.1 PMBus Electrical Characteristics
          2. 6.19.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.19.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.19.5 Serial Peripheral Interface (SPI)
        1. 6.19.5.1 SPI Controller Mode Timings
          1. 6.19.5.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.19.5.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.19.5.1.3 SPI Controller Mode Timing Requirements
          4. 6.19.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.19.5.2 SPI Peripheral Mode Timings
          1. 6.19.5.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.19.5.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.19.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.19.6 Single Edge Nibble Transmission (SENT)
        1. 6.19.6.1 Introduction
        2. 6.19.6.2 Features
      7. 6.19.7 Local Interconnect Network (LIN)
      8. 6.19.8 EtherCAT SubordinateDevice Controller (ESC)
        1. 6.19.8.1 ESC Features
        2. 6.19.8.2 ESC Subsystem Integrated Features
        3. 6.19.8.3 EtherCAT IP Block Diagram
        4. 6.19.8.4 EtherCAT Electrical Data and Timing
          1. 6.19.8.4.1 EtherCAT Timing Requirements
          2. 6.19.8.4.2 EtherCAT Switching Characteristics
          3. 6.19.8.4.3 EtherCAT Timing Diagrams
      9. 6.19.9 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Error Signaling Module (ESM_C29)
      1. 7.3.1 Introduction
      2. 7.3.2 ESM Subsystem
      3. 7.3.3 System ESM
    4. 7.4  Error Aggregator
      1. 7.4.1 Error Aggregator Modules
      2. 7.4.2 Error Aggregator Interface
    5. 7.5  Memory
      1. 7.5.1 C29x Memory Map
      2. 7.5.2 Flash Memory Map
        1. 7.5.2.1 Flash MAIN Region Address Map (F29H85x, 4MB)
        2. 7.5.2.2 Flash MAIN Region Address Map (F29H85x, 2MB)
        3. 7.5.2.3 Flash MAIN Region Address Map (F29P58x, 4MB)
        4. 7.5.2.4 Flash MAIN Region Address Map (F29P58x, F29P32x 2MB)
        5. 7.5.2.5 Flash Data Bank Address Map
        6. 7.5.2.6 Flash BANKMGMT Region Address Map
        7. 7.5.2.7 Flash SECCFG Region Address Map
      3. 7.5.3 Peripheral Registers Memory Map
    6. 7.6  Identification
    7. 7.7  Boot ROM
      1. 7.7.1 Device Boot Sequence
      2. 7.7.2 Device Boot Modes
        1. 7.7.2.1 Default Boot Modes
        2. 7.7.2.2 Custom Boot Modes
      3. 7.7.3 Device Boot Configurations
        1. 7.7.3.1 Configuring Boot Mode Pins
        2. 7.7.3.2 Configuring Boot Mode Table Options
      4. 7.7.4 Device Boot Flow Diagrams
        1. 7.7.4.1 Device Boot Flow
        2. 7.7.4.2 CPU1 Boot Flow
        3. 7.7.4.3 Emulation Boot Flow
        4. 7.7.4.4 Stand-alone Boot Flow
      5. 7.7.5 GPIO Assignments
    8. 7.8  Security Modules and Cryptographic Accelerators
      1. 7.8.1 Security Modules
        1. 7.8.1.1 Hardware Security Module (HSM)
        2. 7.8.1.2 Cryptographic Accelerators
      2. 7.8.2 Safety and Security Unit (SSU)
        1. 7.8.2.1 System View
    9. 7.9  C29x Subsystem
      1. 7.9.1 C29 CPU Architecture
      2. 7.9.2 Peripheral Interrupt Priority and Expansion (PIPE)
        1. 7.9.2.1 Introduction
          1. 7.9.2.1.1 Features
          2. 7.9.2.1.2 Interrupt Concepts
        2. 7.9.2.2 Interrupt Controller Architecture
          1. 7.9.2.2.1 Dynamic Priority Arbitration Block
          2. 7.9.2.2.2 Post Processing Block
          3. 7.9.2.2.3 Memory-Mapped Registers
        3. 7.9.2.3 Interrupt Propagation
      3. 7.9.3 Data Logging and Trace (DLT)
        1. 7.9.3.1 Introduction
          1. 7.9.3.1.1 Features
            1. 7.9.3.1.1.1 Block Diagram
      4. 7.9.4 Waveform Analyzer Diagnostics (WADI)
        1. 7.9.4.1 WADI Overview
          1. 7.9.4.1.1 Features
          2. 7.9.4.1.2 Block Diagram
          3. 7.9.4.1.3 Description
      5. 7.9.5 Embedded Real-Time Analysis and Diagnostic (ERAD)
      6. 7.9.6 Inter-Processor Communications (IPC)
        1. 7.9.6.1 Introduction
      7. 7.9.7 Watchdog
      8. 7.9.8 Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9 Configurable Logic Block (CLB)
    10. 7.10 Lockstep Compare Module (LCM)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2.     TRAY

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZS|100
  • PTS|176
  • RFS|144
  • ZEX|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 lists the features of the F29x devices.

Table 4-1 Device Comparison
FEATURE(1) AUTOMOTIVE COMMERCIAL
H859Tx8 H859Dx6 P589Dx5 P329Sxx(8) H850Tx9 H850Dx7 H850Dx6 H850Dx4 H850Dx3 P580Dx5
H859TU8 H859TM8 H859DU6 P589DU5 P589DM5 P329SJ1 P329SM1 P329SM2 H850TU9 H850DU7 H850DM7 H850DM6 H850DM4 H850DM3 P580DM5
C29x CPU Subsystem
C29x – CPU1 32-bit Floating Point and Trig Instructions 200MHz 200MHz
C29x – CPU2 32-bit Floating Point and Trig Instructions 200MHz – 200MHz Lockstep 200MHz – 200MHz
C29x – CPU3 64-bit Floating Point and Trig Instructions 200MHz – 200MHz –
Lockstep capable (CPU1 can lockstep with CPU2) Configurable – Configurable Fixed Configurable – Configurable
RAM (ECC) M0 (Shared CPU1/CPU2/CPU3) 4KB 4KB 4KB
LPAx (Program optimized CPU1/CPU2) 64KB 64KB 64KB
LDAx (Data optimized CPU1/CPU2, shared with HSM) 128KB 128KB 128KB
CPAx (Program optimized CPU1/CPU3) 64KB 64KB 64KB
CDAx (Data optimized CPU1/CPU3) 192KB – 192KB –
Total 452KB 260KB 452KB 260KB
Flash (ECC) C29x – CPU1/CPU3 4MB 2MB 4MB 4MB 2MB 1MB 2MB 4MB 4MB 2MB
Data Bank (Supports Software EEPROM Emulation) 256KB 128KB 256KB
Firmware Over the Air (FOTA) support Yes Yes
Live Firmware Update (LFU) support Yes Yes
C29x System
CPU timers 3 per CPU 3 per CPU
Real-Time DMA (RTDMA) – 10 Channels Each 2 (Lockstep capable) 1 2 (Lockstep capable)
Data-log and Trace (DLT) – Type 0 1 per CPU 1 per CPU
Enhanced Real-time Analysis and Diagnostic (ERAD) – Type 5 1 per CPU 1 per CPU
External Memory Interface (EMIF)(2) – 1 – 1 –
Embedded Pattern Generator (EPG) Yes Yes
Waveform Analysis and Diagnostic IP (WADI) 2 Instances with 4 blocks – 2 Instances with 4 blocks
Windowed Watchdog Timer (WWD) 1 per CPU 1 per CPU
Dual-clock Comparator (DCC) 3 1 3
Safety and Security
Functional Safety Capability(3) ASIL D/SIL 3 (targeted) ASIL B/SIL 2 (targeted)(6)
ASIL D/SIL 3 (targeted)(6)		 ASIL D/SIL 3 (targeted) ASIL D/SIL 3 (targeted) ASIL B/SIL 2 (targeted)(6)
ASIL D/SIL 3 (targeted)(6)		 – ASIL D/SIL 3 (targeted)
Error Signaling Module (ESM) Yes Yes
Hardware Security Module (HSM) with EVITA-full Yes [see the Hardware Security Module (HSM) section] Yes [see the Hardware Security Module (HSM) section]
JTAG Lock Yes Yes
Logic Power-on Self-test (LPOST) Yes Yes
Memory Power-on Self-test (MPOST) Yes Yes
Safety and Security (SSU) module Yes Yes
SSU Access Protection Regions (APR) 64 per CPU 64 per CPU
Hardware Security Manager (HSM) Subsystem
Cortex-M4 100MHz 100MHz
Nested Vectored Interrupt Controller (NVIC) 64 Interrupts 64 Interrupts
HSM Real-Time DMA (RTDMA) – 8 Channels 1 1
HSM Error Signaling Module (HSM-ESM) Yes Yes
Dual-clock Comparator (DCC) 1 1
Dual Mode Timer (DMTimer) 2 2
Real-time Clock (RTC) Counter 1 1
Real-time Interrupt (RTI) Timer 1 1
Secure Boot Yes Yes No Yes
HSM Windowed Watchdog Timer 1 1
Security Manager Yes Yes
Flash HSM 512KB 256KB 512KB
Firmware Over the Air (FOTA) support Yes Yes
RAM Local 36KB 36KB
LDAx (Shared with C29x) 128KB 128KB
Mailbox 4KB 4KB
Cryptographic Accelerators (Mappable to HSM or C29x)
True Random Number Generator (TRNG) Yes Yes No Yes
Deterministic Random Bit Generator (DRBG) Yes Yes No Yes
CRC Engine Yes Yes No Yes
Symmetric Cryptography Advance Encryption Standard (AES) Yes Yes No Yes
SM4 Yes Yes No Yes
Asymmetric Cryptography Public Key Accelerator (PKA): ECC, RSA Yes Yes No Yes
SM2 Yes Yes No Yes
Hashing Function Hash-based Message Authentication Codes (HMAC) Yes Yes No Yes
Secure Hash Algorithm (SHA) Yes Yes No Yes
MD5 Yes Yes No Yes
SM3 Yes Yes No Yes
GPIO Pins, Analog Pins, and Power Supply
Internal 3.3-V to 1.25-V Voltage Regulator – 100-pin (100MHz) only(4) – 100-pin (100MHz) only(4)
Digital GPIO 256-ball ZEX BGA 110 – 110 – 110 – 110
176-pin PTS HTQFP 86 – 86 – 86 – 86
144-pin RFS HTQFP 65 65 – 85
100-pin PZS HTQFP 46 – 46
Analog or Digital
Bi-directional (AGPIO)		 256-ball ZEX BGA 26 – 26 – 26 – 26
176-pin PTS HTQFP 26 – 26 – 26 – 26
144-pin RFS HTQFP 16 16 – 16
100-pin PZS HTQFP 8 – 8
Analog or Digital Input (AIO) 256-ball ZEX BGA 54 – 54 – 54 – 54
176-pin PTS HTQFP 28 – 28 – 28 – 28
144-pin RFS HTQFP 28 28 – 28
100-pin PZS HTQFP 16 – 16
Total Signal pins (GPIO, AGPIO and AIO) 256-ball ZEX BGA 190 – 190 – 190 – 190
176-pin PTS HTQFP 140 – 140 – 140 – 140
144-pin RFS HTQFP 109 109 – 109
100-pin PZS HTQFP 70 – 70
Analog Peripherals(7)
ADC 16/12-bit Modules ADC AB –
Type 4		 Number 2 2 0 2
16-bit mode Throughput 1.19MSPS – 1.19MSPS
16-bit mode Conversion Time(5) 840ns – 840ns
12-bit mode Throughput 3.92MSPS – 3.92MSPS
12-bit mode Conversion Time(5) 255ns – 255ns
ADC 12-bit Modules ADC CDE –
Type 5		 Number 3 3
ADC A,B,C		 4
ADC A,B,C,D		 3
Throughput 3.92MSPS 3.95MSPS 3.92MSPS
Conversion Time(5) 255ns 253ns 255ns
ADC channels (16-bit single-ended mode)
Modules ADC AB		 256-ball ZEX BGA 32 0 32 – 32
176-pin PTS HTQFP 26 0 26 – 26
144-pin RFS HTQFP 21 0 21 – 21
100-pin PZS HTQFP 12 0 – 12
ADC channels (differential mode)
Modules ADC AB		 256-ball ZEX BGA 16 0 16 – 16
176-pin PTS HTQFP 13 0 13 – 13
144-pin RFS HTQFP 10 0 10 – 10
100-pin PZS HTQFP 6 0 – 6
ADC channels (12-bit single-ended mode)
All ADC Modules		 256-ball ZEX BGA 80 – 80 – 80
176-pin PTS HTQFP 54 – 54 – 54
144-pin RFS HTQFP 44 44 – 44
100-pin PZS HTQFP 24 – 24
Temperature sensor 1 1
Buffered DAC – Type 1 2 – 2
CMPSS (two comparators and two internal DACs) – Type 6 12 1 4 12
Control Peripherals(7)
Configurable Logic Block (CLB) – Type 3 6 Tiles 4 Tiles – 6 Tiles 4 Tiles
ePWM – Type 5 Total Channels 36 24 16 36 24
HRPWM Capable 36 24 – 16 36 24
eCAP – Type 3 Total Modules 6 6 4 6 6
HRCAP Capable 2 (eCAP5, eCAP6) – 2 (eCAP5, eCAP6) –
eQEP modules – Type 2 6 4 6 4
Sigma-Delta Filter Module (SDFM) Channels – Type 2 16 Channels (4 SDFM modules) – 16 Channels (4 SDFM modules)
Communication Peripherals(7)
CAN with Flexible Data-Rate (CAN FD) – Type 2 6 4 3 6 4
Ethernet for Control Automation Technology (EtherCAT)(2) – 1 – 1 –
Fast Serial Interface (FSI) RX – Type 2 4 3 2 4 3
Fast Serial Interface (FSI) TX – Type 2 4 3 2 4 3
Inter-Integrated Circuit (I2C) – Type 2 2 2
LIN – Type 1 (UART-Compatible) 2 2
Power Management Bus (PMBus) 1.1 – Type 0 1 1 1
High Speed UART (HS-UART) – Type 1 6 4 2 6 4
Single Edge Nibble Transmission (SENT) – Type 1 6 4 6
SPI – Type 2 5 5
Package Options, Temperature, and Qualification
Q and S Temperature Codes AEC-Q100 Qualification Grade 1 –
Junction temperature (TJ) –40°C to 150°C –40°C to 150°C
Free-Air temperature (TA) –40°C to 125°C –40°C to 125°C
Package Options 256 ZEX
176 PTS
144 RFS
100 PZS		 144 RFS
100 PZS		 256 ZEX
176 PTS
144 RFS
100 PZS		 256 ZEX
176 PTS
144 RFS
100 PZS		 256 ZEX
176 PTS
144 RFS
100 PZS		 144 RFS
100 PZS		 176 PTS
144 RFS 		176 PTS
144 RFS 		176 PTS
144 RFS 		100 PZS 100 PZS 176 PTS
144 RFS		 176 PTS
144 RFS 100 PZS
T Temperature Codes Junction temperature (TJ) – –40°C to 125°C
Free-Air temperature (TA) – –40°C to 105°C
Package Options – 256 ZEX 256 ZEX 256 ZEX – – 256 ZEX 256 ZEX
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time Microcontrollers Peripherals Reference Guide.
(2) In the 144-pin package, EMIF and EtherCAT cannot be used concurrently.
(3) Supported only with external VREG
(4) VREG is supported on 100-pin devices, but CPU has to run at 100MHz due to current limitations.
(5) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(6) With software-based safety mechanisms like Reciprocal Comparison by software or Coded Processing, however implementation and quality of comparison for such mechanisms is application specific and needs to be decided by system integrator to justify safety integrity levels up to ASIL D/SIL 3.
(7) Module serialization for F29P58x and F29P32x GPNs always starts with smallest number (1) or letter (A) and increments accordingly.
(8) F29P329Sxx devices are Preview information (not Advance Information).