SLASE82A June   2015  – July 2015 HD3SS3411-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
      1. 8.4.1 AC Coupling Capacitors
    5. 8.5 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Routes
      2. 10.1.2 General Routing/Placement Rules
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Critical Routes

  • The high speed differential signals must be routed with great care to minimize signal quality degradation between the connector and the source or sink of the high speed signals by following the guidelines provided in this document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum speed of 10 Gbps. These signals are to be routed first before other signals with highest priority.
  • Each differential pair should be routed together with controlled differential impedance of 85-Ω to 90-Ω and 50-Ω common mode impedance. Keep away from other high speed signals. The number of vias should be kept to minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90 degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of the bend should be greater than 135 degrees.
  • Length matching:
    • Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum. The inter-pair matching of the differential pairs is not as critical as intra-pair matching.
  • Keep high speed differential pair traces adjacent to ground plane.
  • Do not route differential pairs over any plane split.
  • ESD components on the high speed differential lanes should be placed nearest to the connector in a pass through manner without stubs on the differential path.
  • For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS3411-Q1 pins can be swapped.

General Routing/Placement Rules

  • Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the plane.
  • Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines.
  • All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via next to signal via. Distance between ground reference via and signal need to be calculated to have similar impedance as traces.
  • All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing plane splits.
  • Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high frequency return current path.
  • Route differential traces over a continuous plane with no interruptions.
  • Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or any magnetic source.
  • Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep out distance where possible.
  • Decoupling caps should be placed next to each power terminal on the HD3SS3411-Q1. Care should be taken to minimize the stub length of the trace connecting the capacitor to the power pin.
  • Avoid sharing vias between multiple decoupling caps.
  • Place vias as close as possible to the decoupling cap solder pad.
  • Widen VCC/GND planes to reduce effect of static and dynamic IR drop.

Layout Example

HD3SS3411-Q1 Layout_slase82.gif Figure 9. Layout