SNAS678B May 2018 – May 2019 HDC2080
When multiple bits are enabled, the DRDY/INT pin can only reflect the status of one interrupt bit at a time. The DRDY/INT pin DOES NOT function as the logical ‘OR’ of interrupt bits that have been enabled.
The highest priority is given to TH_ENABLE bit, followed by TL_ENABLE, HH_ENABLE, and HL_ENABLE bits in descending order. Therefore, programming recommendations are provided as below: