SBOS859B March   2018  – July 2018 INA1620


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      INA1620 Simplified Internal Schematic
      2.      FFT: 1 kHz, 32-Ω Load, 50 mW
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Matched Thin-Film Resistor Pairs
      2. 7.3.2 Power Dissipation
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 EN Pin
      5. 7.3.5 GND Pin
      6. 7.3.6 Input Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Output Transients During Power Up and Power Down
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
      2. 8.1.2 Resistor Tolerance
      3. 8.1.3 EMI Rejection
      4. 8.1.4 EMIRR +IN Test Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Other Application Examples
      1. 8.3.1 Preamplifier for Professional Microphones
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. TINA-TI (Free Software Download)
        2. TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Figure 55 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configured as a difference amplifier that converts the differential output voltage to single-ended.

The gain of the difference amplifier in Figure 55 is determined by the resistor values, and includes the output impedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shown in Equation 6:

Equation 6. INA1620 ai_typapp_eq1.gif

The output voltage required for headphones depends on the headphone impedance, as well as the headphone efficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level (typically given at 1 mW). The headphone SPL at other power levels is calculated using Equation 7:

Equation 7. INA1620 ai_typapp_eq2.gif


  • η = efficiency
  • PIN = input power to the headphones

Figure 56 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically, over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.

INA1620 ai_C321_SBOS727.pngFigure 56. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies

In-ear headphones can have efficiencies of 115 dB/mW or greater, and therefore have much lower power requirements. The output power goal for this design is 150 mW — sufficient power to produce extremely loud sound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for this requirement because 32 Ω is a very common value in headphones for portable applications. Equation 8 shows the voltage required for 32-Ω headphones:

Equation 8. INA1620 ai_typapp_eq3.gif

Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interfering signals. The maximum value of these capacitors is determined by the limitations on frequency response magnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 to form a pole, as shown in Equation 9:

Equation 9. INA1620 ai_typapp_eq5.gif

Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements using Equation 10:

Equation 10. INA1620 ai_typapp_eq7.gif


  • G represents the gain in decimal for a –0.01-dB deviation at 20 kHz.

Use Equation 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimal magnitude deviation at 20 kHz.

Equation 11. INA1620 ai_eq100.gif

For this design, 100-pF capacitors were used because they meet the design requirements for amplitude deviation in the audio bandwidth.