SLYS017C April   2018  – April 2020 INA180-Q1 , INA2180-Q1 , INA4180-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions: INA180-Q1 (Single Channel)
    2.     Pin Functions: INA2180-Q1 (Dual Channel) and INA4180-Q1 (Quad Channel)
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 High Bandwidth and Slew Rate
      2. 8.3.2 Wide Input Common-Mode Voltage Range
      3. 8.3.3 Precise Low-Side Current Sensing
      4. 8.3.4 Rail-to-Rail Output Swing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Input Differential Overload
      3. 8.4.3 Shutdown Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 RSENSE and Device Gain Selection
      3. 9.1.3 Signal Filtering
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Common-Mode Transients Greater Than 26 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Filtering

Provided that the INAx180-Q1 output is connected to a high impedance input, the best location to filter is at the device output using a simple RC network from OUT to GND. Filtering at the output attenuates high-frequency disturbances in the common-mode voltage, differential input signal, and INAx180-Q1 power-supply voltage. If filtering at the output is not possible, or filtering of only the differential input signal is required, it is possible to apply a filter at the input pins of the device. Figure 46 provides an example of how a filter can be used on the input pins of the device.

INA180-Q1 INA2180-Q1 INA4180-Q1 ai_input-filter_bos741.gifFigure 46. Filter at Input Pins

The addition of external series resistance creates an additional error in the measurement; therefore, the value of these series resistors must be kept to 10 Ω (or less, if possible) to reduce impact to accuracy. The internal bias network shown in Figure 46 present at the input pins creates a mismatch in input bias currents when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch creates a differential error voltage that subtracts from the voltage developed across the shunt resistor. This error results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on device operation. The amount of error these external filter resistors add to the measurement can be calculated using Equation 5, where the gain error factor is calculated using Equation 4.

The amount of variance in the differential voltage present at the device input relative to the voltage developed at the shunt resistor is based both on the external series resistance (RF) value as well as internal input resistor RINT, as shown in Figure 46. The reduction of the shunt voltage reaching the device input pins appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A factor can be calculated to determine the amount of gain error that is introduced by the addition of external series resistance. Calculate the expected deviation from the shunt voltage to what is measured at the device input pins is given using Equation 4:

Equation 4. INA180-Q1 INA2180-Q1 INA4180-Q1 gainerr_factor_bos793.gif


  • RINT is the internal input resistor.
  • RF is the external series resistance.

With the adjustment factor from Equation 4, including the device internal input resistance, this factor varies with each gain version, as shown in Table 1. Each individual device gain error factor is shown in Table 2.

Table 1. Input Resistance

INAx180A1-Q1 20 25
INAx180A2-Q1 50 10
INAx180A3-Q1 100 5
INAx180A4-Q1 200 2.5

Table 2. Device Gain Error Factor

INAx180A1-Q1 INA180-Q1 INA2180-Q1 INA4180-Q1 gainerr_A1_bos793.gif
INAx180A2-Q1 INA180-Q1 INA2180-Q1 INA4180-Q1 gainerr_A2_bos793.gif
INAx180A3-Q1 INA180-Q1 INA2180-Q1 INA4180-Q1 gainerr_A3_bos793.gif
INAx180A4-Q1 INA180-Q1 INA2180-Q1 INA4180-Q1 gainerr_A4_bos793.gif

The gain error that can be expected from the addition of the external series resistors can then be calculated based on Equation 5:

Equation 5. INA180-Q1 INA2180-Q1 INA4180-Q1 q_gainerror_percent_bas437.gif

For example, using an INA180A2-Q1 and the corresponding gain error equation from Table 2, a series resistance of
10 Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 5, resulting in an additional gain error of approximately 0.89% solely because of the external 10-Ω series resistors.