SLYS018C April   2018  – April 2020 INA181-Q1 , INA2181-Q1 , INA4181-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions: INA181-Q1 (Single Channel)
    2.     Pin Functions: INA2181-Q1 (Dual Channel) and INA4181-Q1 (Quad Channel)
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 High Bandwidth and Slew Rate
      2. 8.3.2 Bidirectional Current Monitoring
      3. 8.3.3 Wide Input Common-Mode Voltage Range
      4. 8.3.4 Precise Low-Side Current Sensing
      5. 8.3.5 Rail-to-Rail Output Swing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Unidirectional Mode
      3. 8.4.3 Bidirectional Mode
      4. 8.4.4 Input Differential Overload
      5. 8.4.5 Shutdown Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 RSENSE and Device Gain Selection
      3. 9.1.3 Signal Filtering
      4. 9.1.4 Summing Multiple Currents
      5. 9.1.5 Detecting Leakage Currents
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Common-Mode Transients Greater Than 26 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

at TA = 25°C, VS = 5 V, VREF = VS / 2, VIN+ = 12 V, and VSENSE = VIN+ – VIN– (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection ratio, RTI (1) VIN+ = 0 V to 26 V, VSENSE = 0 mV,
TA = –40°C to +125°C
84 100 dB
VOS Offset voltage, RTI VSENSE = 0 mV ±100 ±500 μV
VSENSE = 0 mV, VIN+ = 0 V ±25 ±150 μV
dVOS/dT Offset drift, RTI VSENSE = 0 mV, TA = –40°C to +125°C 0.2 1 μV/°C
PSRR Power-supply rejection ratio, RTI VS = 2.7 V to 5.5 V, VIN+ = 12 V,
VSENSE = 0 mV
±8 ±40 μV/V
IIB Input bias current VSENSE = 0 mV, VIN+ = 0 V -6 µA
VSENSE = 0 mV 75 µA
IIO Input offset current VSENSE = 0 mV ±0.05 µA
OUTPUT
G Gain A1 devices 20 V/V
A2 devices 50 V/V
A3 devices 100 V/V
A4 devices 200 V/V
EG Gain error VOUT = 0.5 V to VS – 0.5 V,
TA = –40°C to +125°C
±0.1% ±1%
Gain error vs temperature TA = –40°C to +125°C 1.5 20 ppm/°C
Nonlinearity error VOUT = 0.5 V to VS – 0.5 V ±0.01%
Maximum capacitive load No sustained oscillation 1 nF
VOLTAGE OUTPUT (2)
VSP Swing to VS power-supply rail(1) RL = 10 kΩ to GND, TA = –40°C to +125°C (VS) – 0.02 (VS) – 0.03 V
VSN Swing to GND(1) RL = 10 kΩ to GND, TA = –40°C to +125°C (VGND) + 0.0005 (VGND) + 0.005 V
FREQUENCY RESPONSE
BW Bandwidth A1 devices, CLOAD = 10 pF 350 kHz
A2 devices, CLOAD = 10 pF 210 kHz
A3 devices, CLOAD = 10 pF 150 kHz
A4 devices, CLOAD = 10 pF 105 kHz
SR Slew rate 2 V/µs
NOISE, RTI(1)
Voltage noise density 40 nV/√Hz
POWER SUPPLY
IQ Quiescent current INA181-Q1 VSENSE = 0 mV 195 260 µA
VSENSE = 0 mV, TA = –40°C to +125°C 300 µA
INA2181-Q1 VSENSE = 0 mV 356 500 µA
VSENSE = 0 mV, TA = –40°C to +125°C 520 µA
INA4181-Q1 VSENSE = 0 mV 690 900 µA
VSENSE = 0 mV, TA = –40°C to +125°C 1000 µA
RTI = referred-to-input.
See Figure 19.
Swing specifications are tested with an overdriven input condition.