A simplified version of the delay circuit for Comparator 2 is shown in Figure 7-4. The delay comparator consists of two comparator stages with the delay between them. I1 and I2 cannot be turned on simultaneously; I1 corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1 output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to CDELAY. The voltage at U2 +IN begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of the delay specified for CDELAY). This entire sequence is reversed when the comparator outputs go low, so that returning to low exhibits the same delay.
Take care to note what will happen if events occur more rapidly than the delay timeout; for example, when the U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6-V transition for U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to zero if given sufficient time.
In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the model shown in Figure 7-4.