SBOS601A February   2012  – December 2021 INA230

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements (I2C)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Power Calculation
      3. 8.3.3 Alert Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
      2. 8.4.2 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the Calibration Register
      2. 8.5.2 Programming the INA230 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA230 Settings
      5. 8.5.5 Bus Overview
        1. 8.5.5.1 Serial Bus Address
        2. 8.5.5.2 Serial Interface
      6. 8.5.6 Writing to and Reading From the I2C Serial Interface
        1. 8.5.6.1 High-Speed I2C Mode
      7. 8.5.7 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h, Read/Write)
      2. 8.6.2 AVG Bit Settings [11:9]
      3. 8.6.3 VBUS CT Bit Settings [8:6]
      4. 8.6.4 VSH CT Bit Settings [5:3]
      5. 8.6.5 Mode Settings [2:0]
      6. 8.6.6 Data Output Register
        1. 8.6.6.1 Shunt Voltage Register (01h, Read-Only)
        2. 8.6.6.2 Bus Voltage Register (02h, Read-Only) (1)
        3. 8.6.6.3 Power Register (03h, Read-Only)
        4. 8.6.6.4 Current Register (04h, Read-Only)
        5. 8.6.6.5 Calibration Register (05h, Read/Write)
        6. 8.6.6.6 Mask/Enable Register (06h, Read/Write)
        7. 8.6.6.7 Alert Limit Register (07h, Read/Write)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Sensing Circuit Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • DGS|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.6 Writing to and Reading From the I2C Serial Interface

Accessing a specific register on the INA230 is accomplished by writing the appropriate value to the register pointer. Refer to Section 8.6 for a complete list of registers and corresponding addresses. The value for the register pointer (see Figure 8-7) is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the controller is the address of the register to be accessed. This register address value updates the register pointer to the desired internal device register. The next two bytes are written to the register addressed by the register pointer. The device acknowledges receipt of each data byte. The controller may terminate data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a target address byte with the R/W bit low, followed by the register pointer byte. No additional data are required. The controller then generates a start condition and sends the address byte for the target with the R/W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the controller, then the target transmits the least significant byte. The controller may or may not acknowledge receipt of the second data byte. The controller may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the device retains the register pointer value until it is changed by the next write operation.

Figure 8-4 shows the write operation timing diagram. Figure 8-5 shows the read operation timing diagram. These diagrams are shown for reading/writing to 16-bit registers.

Register bytes are sent most-significant byte first, followed by the least significant byte.

(1) The value of the Target Address byte is determined by the setting of the address pins. Refer to Table 8-2.

(2) The device does not support packet error checking (PEC) or perform clock stretching.

Figure 8-4 Timing Diagram for Write Word Format

(1) The value of the Target Address byte is determined by the setting of the address pins. Refer to Table 8-2.

(2) Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 8-7.

(3) ACK by the controller can also be sent.

(4) The device does not support packet error checking (PEC) or perform clock stretching.

Figure 8-5 Timing Diagram for Read Word Format

Figure 8-6 shows the timing diagram for the SMBus Alert response operation. Figure 8-7 shows a typical register pointer configuration.

(1) The value of the Target Address byte is determined by the setting of the address pins. Refer to Table 8-2.

Figure 8-6 Timing Diagram for SMBus ALERT

(1) The value of the Target Address byte is determined by the setting of the address pins. Refer to Table 8-2.

Figure 8-7 Typical Register Pointer Set