SBOS644C February   2013  – March 2018 INA231

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      High-or Low-Side Sensing
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: I2C Bus
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic Analog-to-Digital Converter (ADC) Functions
        1. 8.3.1.1 Power Calculation
        2. 8.3.1.2 ALERT Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
    5. 8.5 Programming
      1. 8.5.1 Configure, Measure, and Calculate Example
      2. 8.5.2 Programming the Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA231 Settings
      5. 8.5.5 Writing to and Reading from the INA231
        1. 8.5.5.1 Bus Overview
          1. 8.5.5.1.1 Serial Bus Address
          2. 8.5.5.1.2 Serial Interface
        2. 8.5.5.2 High-Speed I2C Mode
      6. 8.5.6 SMBus Alert Response
    6. 8.6 Register Maps
      1. Table 3. Summary of Register Set
      2. 8.6.1     Configuration Register (00h, Read/Write)
        1. Table 4. Configuration Register (00h, Read/Write) Descriptions
        2. 8.6.1.1   AVG Bit Settings [11:9]
          1. Table 5. AVG Bit Settings [11:9] Description
        3. 8.6.1.2   VBUS CT Bit Settings [8:6]
          1. Table 6. VBUS CT Bit Settings [8:6] Description
        4. 8.6.1.3   VSH CT Bit Settings [5:3]
          1. Table 7. Register Description VSH CT Bit Settings [5:3]
        5. 8.6.1.4   Mode Settings [2:0]
          1. Table 8. Mode Settings [2:0]
      3. 8.6.2     Shunt Voltage Register (01h, Read-Only)
        1. Table 9. Shunt Voltage Register (01h, Read-Only) Description
      4. 8.6.3     Bus Voltage Register (02h, Read-Only)
        1. Table 10. Bus Voltage Register (02h, Read-Only) Description
      5. 8.6.4     Power Register (03h, Read-Only)
        1. Table 11. Power Register (03h, Read-Only) Description
      6. 8.6.5     Current Register (04h, Read-Only)
        1. Table 12. Current Register (04h, Read-Only) Description
      7. 8.6.6     Calibration Register (05h, Read/Write)
        1. Table 13. Calibration Register (05h, Read/Write) Description
      8. 8.6.7     Mask/Enable Register (06h, Read/Write)
        1. Table 14. Mask/Enable Register (06h, Read/Write) Description
      9. 8.6.8     Alert Limit Register (07h, Read/Write)
        1. Table 15. Alert Limit Register (07h, Read/Write) Description
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filtering and Input Considerations
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|12
  • YFD|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Mask/Enable Register (06h, Read/Write)

The Mask/Enable register selects the function that controls the ALERT pin, as well as how that pin functions. If multiple functions are enabled, the highest significant bit position alert function (D15:D11) takes priority and responds to the Alert Limit register.

Table 14. Mask/Enable Register (06h, Read/Write) Description

BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BIT
NAME
SOL SUL BOL BUL POL CNVR AFF CVRF OVF APOL LEN
POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SOL: Shunt Voltage Overvoltage1
Bit 15 Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion exceeds the value in the Alert Limit register.
SUL: Shunt Voltage Undervoltage
Bit 14 Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion drops below the value in the Alert Limit register.
BOL: Bus Voltage Overvoltage
Bit 13 Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion exceeds the value in the Alert Limit register.
BUL: Bus Voltage Undervoltage
Bit 12 Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion drops below the value in the Alert Limit register.
POL: Power Overlimit
Bit 11 Setting this bit high configures the ALERT pin to be asserted when the power calculation exceeds the value in the Alert Limit register.
CNVR: Conversion Ready
Bit 10 Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag bit (CVRF, bit 3) is asserted, indicating that the device is ready for the next conversion.
AFF: Alert Function Flag
Bit 4 Although only one alert function at a time can be monitored at the ALERT pin, the Conversion Ready bit (CNVR, bit 10) can also be enabled to assert the ALERT pin. Reading the Alert Function Flag bit after an alert can help determine if the alert function was the source of the alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared after the next conversion that does not result in an alert condition.

CVRF: Conversion Ready Flag
Bit 3 Although the INA231 can be read at any time, and the data from the last conversion are available, this bit is provided to help coordinate single-shot or triggered conversions. This bit is set after all conversions, averaging, and multiplications are complete. This bit clears under the following conditions in single-shot mode:

1) Writing to the Configuration register (except for power-down or disable selections)

2) Reading the Mask/Enable register

OVF: Math Overflow Flag
Bit 2 This bit is set to 1 if an arithmetic operation results in an overflow error; it indicates that current and power data may be invalid.
APOL: Alert Polarity
Bit 1

Configures the latching feature of the ALERT pin and the flag bits.


1 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)
LEN: Alert Latch Enable
Bit 0

Configures the latching feature of the ALERT pin and flag bits.

1 = Latch enabled
0 = Transparent (default)

When the Alert Latch Enable bit is set to Transparent mode, the ALERT pin and flag bits reset to their idle states when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and flag bits remain active following a fault until the Mask/Enable register has been read.