SBOS644C February   2013  – March 2018 INA231

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      High-or Low-Side Sensing
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: I2C Bus
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic Analog-to-Digital Converter (ADC) Functions
        1. 8.3.1.1 Power Calculation
        2. 8.3.1.2 ALERT Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
    5. 8.5 Programming
      1. 8.5.1 Configure, Measure, and Calculate Example
      2. 8.5.2 Programming the Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA231 Settings
      5. 8.5.5 Writing to and Reading from the INA231
        1. 8.5.5.1 Bus Overview
          1. 8.5.5.1.1 Serial Bus Address
          2. 8.5.5.1.2 Serial Interface
        2. 8.5.5.2 High-Speed I2C Mode
      6. 8.5.6 SMBus Alert Response
    6. 8.6 Register Maps
      1. Table 3. Summary of Register Set
      2. 8.6.1     Configuration Register (00h, Read/Write)
        1. Table 4. Configuration Register (00h, Read/Write) Descriptions
        2. 8.6.1.1   AVG Bit Settings [11:9]
          1. Table 5. AVG Bit Settings [11:9] Description
        3. 8.6.1.2   VBUS CT Bit Settings [8:6]
          1. Table 6. VBUS CT Bit Settings [8:6] Description
        4. 8.6.1.3   VSH CT Bit Settings [5:3]
          1. Table 7. Register Description VSH CT Bit Settings [5:3]
        5. 8.6.1.4   Mode Settings [2:0]
          1. Table 8. Mode Settings [2:0]
      3. 8.6.2     Shunt Voltage Register (01h, Read-Only)
        1. Table 9. Shunt Voltage Register (01h, Read-Only) Description
      4. 8.6.3     Bus Voltage Register (02h, Read-Only)
        1. Table 10. Bus Voltage Register (02h, Read-Only) Description
      5. 8.6.4     Power Register (03h, Read-Only)
        1. Table 11. Power Register (03h, Read-Only) Description
      6. 8.6.5     Current Register (04h, Read-Only)
        1. Table 12. Current Register (04h, Read-Only) Description
      7. 8.6.6     Calibration Register (05h, Read/Write)
        1. Table 13. Calibration Register (05h, Read/Write) Description
      8. 8.6.7     Mask/Enable Register (06h, Read/Write)
        1. Table 14. Mask/Enable Register (06h, Read/Write) Description
      9. 8.6.8     Alert Limit Register (07h, Read/Write)
        1. Table 15. Alert Limit Register (07h, Read/Write) Description
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filtering and Input Considerations
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|12
  • YFD|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Serial Interface

The INA231 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although there is spike suppression integrated into the digital I/O lines, use proper layout to minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitively coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielding communication lines in general is recommended to reduce to possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.

The INA231 supports the transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 2.5 MHz) modes. All data bytes are transmitted most significant byte first.

Accessing a specific register on the INA231 is accomplished by writing the appropriate value to the register pointer. Refer to Table 3 for a complete list of registers and corresponding addresses. The value for the register pointer (shown in Figure 26) is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the INA231 requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit low. The INA231 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA231 acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop condition.

When reading from the INA231, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an ACK from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge bit (No ACK) after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA231 retains the register pointer value until it is changed by the next write operation.

Figure 23 and Figure 24 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

INA231 ai_tim_wr_word_bos644.gif
The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 23. Timing Diagram for Write Word Format
INA231 ai_tim_rd_word_bos644.gif
The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 26.
ACK by Master can also be sent.
Figure 24. Timing Diagram for Read Word Format

Figure 25 shows the timing diagram for the SMBus alert response operation. Figure 26 illustrates a typical register pointer configuration.

INA231 ai_tim_smbus_bos644.gif
The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 25. Timing Diagram for SMBus Alert
INA231 ai_tim_typ_pointer_bos644.gif
The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 2.
Figure 26. Typical Register Pointer Set