SBOS511B April   2015  – December 2015


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Shunt Resistor
      2. 7.3.2 Short-Circuit Duration
      3. 7.3.3 Temperature Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Amplifier Operation
      2. 7.4.2 Input Filtering
        1. Calculating Gain Error Resulting from External Filter Resistance
      3. 7.4.3 Shutting Down the Device
      4. 7.4.4 Using the Device with Common-Mode Transients Above 36 V
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Current Summing
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 8.2.2 Parallel Multiple INA250 Devices for Higher Current
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 8.2.3 Current Differencing
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Applications and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The INA250 measures the voltage developed across the internal current-sensing resistor when current passes through it. The ability to drive the reference pin to adjust the functionality of the output signal offers multiple configurations, as discussed in this section.

8.2 Typical Applications

8.2.1 Current Summing

INA250A1 INA250A2 INA250A3 INA250A4 ai_sum_bos511.gif Figure 37. Daisy-Chain Configuration Design Requirements

Three daisy-chained devices are illustrated in Figure 37. The reference input of the first INA250 sets the quiescent level on the output of all the INA250 devices in the string. Detailed Design Procedure

The outputs of multiple INA250 devices are easily summed by connecting the output signal of one INA250 to the reference input of a second INA250. Summing beyond two devices is possible by repeating this configuration, connecting the output signal of the next INA250 to the reference pin of a subsequent INA250 in the chain. The output signal of the final INA250 in this chain includes the current level information for all channels in the chain. Application Curve

INA250A1 INA250A2 INA250A3 INA250A4 C034_SBOS511.png
VS = 5 V, VREF = 2.5 V
Figure 38. Daisy-Chain Configuration Output Response

8.2.2 Parallel Multiple INA250 Devices for Higher Current

INA250A1 INA250A2 INA250A3 INA250A4 ai_parallel_bos511.gif Figure 39. Parallel Summing Configuration Design Requirements

The parallel connection for multiple INA250 devices can be used to reduce the equivalent overall sense resistance, enabling monitoring of higher current levels than a single device is able to accommodate alone. This configuration also uses a summing arrangement, as described in the Current Summing section. A parallel summing configuration is shown in Figure 39. Detailed Design Procedure

With a summing configuration the output of the first channel is fed into the reference input of the second, adding the distributed measurements back together into a single measured value. Application Curve

INA250A1 INA250A2 INA250A3 INA250A4 C036_SBOS511.png
VS = 24 V, VREF = 12 V
Figure 40. Parallel Configuration Output Response

8.2.3 Current Differencing

INA250A1 INA250A2 INA250A3 INA250A4 ai_totem-pole_bos511.gif Figure 41. Current Differencing Configuration Design Requirements

Occasionally, the need may arise to confirm that the current into a load is identical to the current coming out of a load, such as when performing diagnostic testing or fault detection. This procedure requires precision current differencing. This method is the same as current summing, except that the two amplifiers have the respective inputs connected opposite of each other. Under normal operating conditions, the final output is very close to the reference value and proportional to any current difference. Figure 41 is an example of two INA250 devices connected for current differencing. Detailed Design Procedure

The load current can also be measured directly at the output of the first channel. Although technically this configuration is current differencing, this connection (see Figure 41) is really intended to allow the upper (positive) sense channel to report any positive-going excursions in the overall output and the lower (negative) sense channel to report any negative-going excursions. Application Curve

INA250A1 INA250A2 INA250A3 INA250A4 C035_SBOS511.png
VS = 5 V, VREF = 2.5 V
Figure 42. Current Differencing Configuration Output Response