The extremely high DC CMRR of the INA28x-Q1 results from the switched capacitor input structure. Because of this architecture, the INA28x-Q1 exhibits discrete time system behaviors as illustrated in the gain versus frequency graph of Figure 6-3 and the step response curves of Figure 6-21 through Figure 6-28. The response to a step input depends somewhat on the phase of the internal INA28x-Q1 clock when the input step occurs. It is possible to overload the input amplifier with a rapid change in input common-mode voltage (see Figure 6-4). Errors as a result of common-mode voltage steps and/or overload situations typically disappear within 15 μs after the disturbance is removed.