SBOS464A October   2019  – May 2020 INA333-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Offset Correction
      2. 7.3.2 Input Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode Range
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Gain
        2. 8.2.2.2 Offset Trimming
        3. 8.2.2.3 Noise Performance
        4. 8.2.2.4 Input Bias Current Return Path
        5. 8.2.2.5 Low Voltage Operation
        6. 8.2.2.6 Single-Supply Operation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Download Software)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
INA333-Q1 tc_histo_in_vo_bos445.gif
Figure 1. Input Offset Voltage
INA333-Q1 tc_histo_out_off_bos445.gif
Figure 3. Output Offset Voltage
INA333-Q1 tc_vos-vcm_bos445.gif
Figure 5. Offset Voltage vs Common-Mode Voltage
INA333-Q1 tc_noise_100g_bos445.gif
Figure 7. 0.1-Hz to 10-Hz Noise
INA333-Q1 tc_inl_err_bos445.gif
Figure 9. Nonlinearity Error
INA333-Q1 tc_lg_resp_100g_bos445.gif
Figure 11. Large-Signal Step Response
INA333-Q1 tc_sm_resp_100g_bos445.gif
Figure 13. Small-Signal Step Response
INA333-Q1 tc_startup_tset_bos445.gif
Figure 15. Start-Up Settling Time
INA333-Q1 tc_histo_cmrr_1g_bos445.gif
Figure 17. Common-Mode Rejection Ratio
INA333-Q1 tc_cmrr-frq_bos445.gif
Figure 19. Common-Mode Rejection Ratio vs Frequency
INA333-Q1 tc_typ_cmr-vo_tri_bos445.gif
Figure 21. Typical Common-Mode Range vs Output Voltage
INA333-Q1 tc_typ_cmr-vo_tri_1p8_bos445.gif
Figure 23. Typical Common-Mode Range vs Output Voltage
INA333-Q1 tc_neg_psrr-frq_bos445.gif
Figure 25. Negative Power-Supply Rejection Ratio
INA333-Q1 tc_in_ib-vcm_bos445.gif
Figure 27. Input Bias Current vs Common-Mode Voltage
INA333-Q1 tc_vo_swing-io_bos445.gif
Figure 29. Output Voltage Swing vs Output Current
INA333-Q1 tc_iq-vcm_bos445.gif
Figure 31. Quiescent Current vs Common-Mode Voltage
INA333-Q1 tc_histo_in_vo_drift_bos445.gif
Figure 2. Input Voltage Offset Drift (–40°C to 125°C)
INA333-Q1 tc_histo_out_vo_drift_bos445.gif
Figure 4. Output Voltage Offset Drift (–40°C to 125°C)
INA333-Q1 tc_noise_1g_bos445.gif
Figure 6. 0.1-Hz to 10-Hz Noise
INA333-Q1 tc_noise_spec_bos445.gif
Figure 8. Spectral Noise Density
INA333-Q1 tc_lg_resp_1g_bos445.gif
Figure 10. Large Signal Response
INA333-Q1 tc_sm_resp_1g_bos445.gif
Figure 12. Small-Signal Step Response
INA333-Q1 tc_tset-g_bos445.gif
Figure 14. Settling Time vs Gain
INA333-Q1 tc_g-frq_bos445.gif
Figure 16. Gain vs Frequency
INA333-Q1 tc_cmrr-tmp_bos445.gif
Figure 18. Common-Mode Rejection Ratio vs Temperature
INA333-Q1 tc_typ_cmr-vo_oct_bos445.gif
Figure 20. Typical Common-Mode Range vs Output Voltage
INA333-Q1 tc_typ_cmr-vo_oct_0p9_bos445.gif
Figure 22. Typical Common-Mode Range vs Output Voltage
INA333-Q1 tc_pos_psrr-frq_bos445.gif
Figure 24. Positive Power-Supply Rejection Ratio
INA333-Q1 tc_in_ib-tmp_bos445.gif
Figure 26. Input Bias Current vs Temperature
INA333-Q1 tc_in_ios-tmp_bos445.gif
Figure 28. Input Offset Current vs Temperature
INA333-Q1 tc_iq-tmp_bos445.gif
Figure 30. Quiescent Current vs Temperature