SBOSAM2 August   2025 INA701

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Shunt Resistor
      2. 6.3.2 Safe Operating Area
      3. 6.3.3 Versatile Measurement Capability
      4. 6.3.4 Internal Measurement and Calculation Engine
      5. 6.3.5 High-Precision Delta-Sigma ADC
        1. 6.3.5.1 Low Latency Digital Filter
        2. 6.3.5.2 Flexible Conversion Times and Averaging
      6. 6.3.6 Integrated Precision Oscillator
      7. 6.3.7 Multi-Alert Monitoring and Fault Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Power-On Reset
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 6.5.1.2 High-Speed I2C Mode
        3. 6.5.1.3 SMBus Alert Response
    6. 6.6 Register Maps
      1. 6.6.1 INA701 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Device Measurement Range and Resolution
      2. 7.1.2 ADC Output Data Rate and Noise Performance
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Configure the Device
        2. 7.2.2.2 Set Desired Fault Thresholds
        3. 7.2.2.3 Calculate Returned Values
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YWF|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.2 Set Desired Fault Thresholds

Fault thresholds are set by programming the desired trip threshold into the corresponding fault register. Table 6-1 shows the list of supported fault registers.

An overcurrent threshold is set by programming the Current Over-Limit Threshold register (COL). The value that must be programmed into this register is calculated by dividing the overcurrent limit value by the current LSB size. For this example, the target value for the COL register is 2A ÷ 190μA = 10526d (291Eh).

An overvoltage fault threshold on the bus voltage is set by programming the bus overvoltage limit register (BOVL). In this example the desired overvoltage threshold is 14V. The value that must be programmed into this register is calculated by dividing the target threshold voltage by the bus voltage fault limit LSB value of 3.125mV. For this example, the target value for the BOVL register is 14V ÷ 3.125mV = 4480d (1180h).

When setting the power over-limit value, the LSB size used to calculate the value needed in the limit registers is 256 times greater than the power LSB. This is because the power register is a 24 bits in length while the power fault limit register is 16 bits. The LSB value to use for setting the over-power fault limit is 9.728mW.

Values stored in the alert limit registers are set to the default values after VS power cycle events and must be reprogrammed each time power is applied.