SBOS894A April   2019  – June 2019 INA818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      INA818 Simplified Internal Schematic
      2.      Typical Distribution of Input Stage Offset Voltage Drift
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics: Table of Graphs
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Setting the Gain
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Operating Voltage
      6. 8.3.6 Error Sources
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Resistance Temperature Detector Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Typical Characteristics: Table of Graphs

Table 1. Table of Graphs

DESCRIPTION FIGURE
Typical Distribution of Input Stage Offset Voltage Figure 1
Typical Distribution of Input Stage Offset Voltage Drift Figure 2
Typical Distribution of Output Stage Offset Voltage Figure 3
Typical Distribution of Output Stage Offset Voltage Drift Figure 4
Input Stage Offset Voltage vs Temperature Figure 5
Output Stage Offset Voltage vs Temperature Figure 6
Typical Distribution of Input Bias Current TA = 25°C Figure 7
Typical Distribution of Input Bias Current TA = 90°C Figure 8
Typical Distribution of Input Offset Current Figure 9
Input Bias Current vs Temperature Figure 10
Input Offset Current vs Temperature Figure 11
Typical CMRR Distribution G = 1 Figure 12
Typical CMRR Distribution G = 10 Figure 13
CMRR vs Temperature G = 1 Figure 14
CMRR vs Temperature G = 10 Figure 15
Input Current vs Input Overvoltage Figure 16
CMRR vs Frequency (RTI) Figure 17
CMRR vs Frequency (RTI, 1-kΩ source imbalance) Figure 18
Positive PSRR vs Frequency (RTI) Figure 19
Negative PSRR vs Frequency (RTI) Figure 20
Gain vs Frequency Figure 21
Voltage Noise Spectral Density vs Frequency (RTI) Figure 22
Current Noise Spectral Density vs Frequency (RTI) Figure 23
0.1-Hz to 10-Hz RTI Voltage Noise G = 1 Figure 24
0.1-Hz to 10-Hz RTI Voltage Noise G = 1000 Figure 25
0.1-Hz to 10-Hz RTI Current Noise Figure 26
Typical Distribution of Gain Error G = 1 Figure 28
Typical Distribution of Gain Error G = 10 Figure 29
Input Bias Current vs Common-Mode Voltage Figure 27
Gain Error vs Temperature G = 1 Figure 30
Gain Error vs Temperature G = 10 Figure 31
.Supply Current vs Temperature Figure 32
Gain Nonlinearity G = 1 Figure 33
Gain Nonlinearity G = 10 Figure 34
Offset Voltage vs Negative Common-Mode Voltage Figure 35
Offset Voltage vs Positive Common-Mode Voltage Figure 36
Positive Output Voltage Swing vs Output Current Figure 37
Negative Output Voltage Swing vs Output Current Figure 38
Short Circuit Current vs Temperature Figure 39
Large-Signal Frequency Response Figure 40
THD+N vs Frequency Figure 41
Overshoot vs Capacitive Loads Figure 42
Small-Signal Response G = 1 Figure 43
Small-Signal Response G = 10 Figure 44
Small-Signal Response G = 100 Figure 45
Small-Signal Response G = 1000 Figure 46
Large Signal Step Response Figure 47
Closed-Loop Output Impedance Figure 48
Differential-Mode EMI Rejection Ratio Figure 49
Common-Mode EMI Rejection Ratio Figure 50
Input Common-Mode Voltage vs Output Voltage G = 1, VS = 5 V Figure 51
Input Common-Mode Voltage vs Output Voltage G = 100, VS = 5 V Figure 52
Input Common-Mode Voltage vs Output Voltage VS =±5 V Figure 53
Input Common-Mode Voltage vs Output Voltage VS =±15 V Figure 54