SBOS959C December   2018  – June 2020 INA819


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      INA819 Simplified Internal Schematic
      2.      Typical Distribution of Input Stage Offset Voltage Drift
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics: Table of Graphs
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Setting the Gain
        1. Gain Drift
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Operating Voltage
      6. 8.3.6 Error Sources
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Resistance Temperature Detector Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Reference Pin

The output voltage of the INA819 is developed with respect to the voltage on the reference pin (REF.) Often, in dual-supply operation, REF (pin 6) is connected to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the output so that the INA819 drives a single-supply analog-to-digital converter (ADC).

The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 65, any resistance at the reference pin (shown as RREF in Figure 65) is in series with an internal 40-kΩ resistor.

INA819 ai_D001_SBOS792.gifFigure 65. Parasitic Resistance Shown at the Reference Pin

The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal difference amplifier that results in a degraded common-mode rejection ratio (CMRR). Figure 66 shows the degradation in CMRR of the INA819 as a result of increased resistance at the reference pin. For the best performance, keep the source impedance to the REF pin (RREF) less than 5 Ω.

INA819 D057_SBOS959.gifFigure 66. The Effect of Increasing Resistance at the Reference Pin

Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op amp, as Figure 67 shows, to avoid CMRR degradation.

INA819 ai_D002_INA819.gifFigure 67. Using an Op Amp to Buffer Reference Voltages