SBOS945B November   2020  – April 2021 INA849

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
      2. 8.3.2 Gain Drift
      3. 8.3.3 Wide Input Common-Mode Range
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
      3. 9.1.3 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Application
      1. 9.2.1 Sensor Conditioning Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Phantom Power in Microphone Preamplifier Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1) (3) 10 35 µV
TA = –40°C to +125°C(2) 75
Input stage offset voltage drift TA = –40°C to +125°C 0.1 0.4 µV/°C
VOSO Output stage offset voltage(1) (3) 50 500 µV
TA = –40°C to +125°C(2) 2000
Output stage offset voltage drift TA = –40°C to +125°C(2) 15 µV/°C
PSRR Power-supply rejection ratio G = 1, RTI 106 120 dB
G = 10, RTI 114 120
G = 100, RTI 121 126
G = 1000, RTI 123 128
Zin Input impedance 1 || 7 GΩ || pF
RFI filter, –3-dB frequency 220 MHz
VCM Operating input range(4) (–VS) + 2.5 (+VS) – 2.5 V
VS = ±4 V to ±18 V See Figure 8-2 and Figure 8-3
CMRR Common-mode rejection ratio At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 1		 92 110 dB
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 10		 112 125
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 100		 120 127
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 1000		 120 127
BIAS CURRENT
IB Input bias current VCM = VS / 2 20 nA
Input bias current drift TA = –40°C to +125°C 10 80 pA/°C
IOS Input offset current VCM = VS / 2 6 nA
Input offset current drift TA = –40°C to +125°C 5 pA/°C
NOISE VOLTAGE
eNI Input stage voltage noise(8) f = 1 kHz, G = 1000,
RS = 0 Ω		 1 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 1000,
RS = 0 Ω		 0.06 µVPP
eNO Output stage voltage noise(8) f = 1 kHz, RS = 0 Ω 45 nV/√Hz
fB = 0.1 Hz to 10 Hz,
RS = 0 Ω		 5 µVPP
iN Current noise f = 1 kHz(9) 1.1 pA/√Hz
fB = 0.1 Hz to 10 Hz 100 pAPP
GAIN
G Gain equation 1 + (6 kΩ / RG) V/V
Gain 1 10000 V/V
GE Gain error  (8) G = 1, VO = ±10 V ±0.005 ±0.025 %
G = 10, VO = ±10 V ±0.025 ±0.1
G = 100, VO = ±10 V ±0.025 ±0.1
G = 1000, VO = ±10 V ±0.05
Gain error drift(5) G = 1, TA = –40°C to +125°C ±5 ppm/°C
G > 1, TA = –40°C to +125°C ±35
Gain nonlinearity G = 1, VO = –10 V to +10 V 3 ppm
G = 10 (7) , VO = –10 V to +10 V 10
THD Total harmonic distortion f = 1 kHz, VO = 10 VPP 127 dBc
HD2 Second-order harmonic distortion f = 1 kHz, VO = 10 VPP 127 dBc
HD3 Third-order harmonic distortion f = 1 kHz, VO = 10 VPP 157 dBc
THD Total harmonic distortion f = 10 kHz, VO = 10 VPP 119 dBc
HD2 Second-order harmonic distortion f = 10 kHz, VO = 10 VPP 130 dBc
HD3 Third-order harmonic distortion f = 10 kHz, VO = 10 VPP 120 dBc
OUTPUT
Voltage swing RL = 10 kΩ (V–) + 0.15 (V+) – 0.15 V
Load capacitance stability 200 pF
ZO Closed-loop output impedance f = 1 MHz 1.5 Ω
ISC Short-circuit current Continuous to VS / 2 ±34 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 28 MHz
G = 10 13
G = 100 8
G = 1000 1.25
SR Slew rate G = 1, VSTEP = 10 V 35 V/µs
tS Settling time 0.01%, G = 1 to 100,
VSTEP = 10 V		 0.4 µs
0.01%, G = 1000,
VSTEP = 10 V		 0.4
0.001%, G = 1 to 100,
VSTEP = 10 V		 0.6
0.001%, G = 1000,
VSTEP = 10 V		 1.5
REFERENCE INPUT
RIN Input impedance 10 kΩ
Input current 80 µA
Reference input voltage (V–) (V+) V
Gain to output 1 V/V
Reference gain error VO = ±10 V, inside the voltage swing range 0.01 0.05 %
POWER SUPPLY
IQ Quiescent current  (8) VIN = 0 V 6.2 6.6 mA
TA = –40°C to +125°C 8.9
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization. Not tested in production.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2]. 
(4) Input voltage range of the input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage; see Figure 7-12.
(5) The values specified for G > 1 do not include the effects of the external gain resistor, RG.
(6) Thermal effects can degrade input stage nonlinearity and thus can scale with gain; See Figure 9-5.
(7) This parameter is tested in a high speed automatic test environment and does not measure the thermal effects with a longer a time constant. The thermal effect depends on supply voltage, layout, heat sinking and air flow conditions.
(8) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].
(9) Input current noise density specified for unbalanced input impedance. Bias current cancellation improves noise performance for balanced systems; See Figure 7-25.