SBOS999A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Output Clamping

The INA851 features a unique output clamping function that protects the downstream device against damage that results from inadvertent over-driving. Usually the downstream device is an ADC that typically operates at a lower supply voltage than the INA851.

To implement this function, use the VCLAMP+ and VCLAMP– pins to limit the supply voltage range of the differential output drive amplifier. For typical operation, use a low-impedance connection from the pins to the power supplies of the ADC. For proper operation of the clamp circuitry, set the VS+ or VS– supply voltages at least 1.5 V beyond the respective VCLAMP+ and VCLAMP– clamping voltages. In addition, for the output driver to function correctly, the VCLAMP+ and VCLAMP– voltages must be at least 3 V apart. If the output clamping functionality is not desired, short the VCLAMP+ and VCLAMP– pins to the amplifier VS+ and VS– supply pins.

The output driver operates up to the VCLAMP+ or VCLAMP– limits without experiencing distortion. When the clamping function is in use the output voltage is clamped at approximately 600 mV beyond the clamp voltage.), so that the device output spans the full input range of the ADC. However, if the predriver output swings beyond the VCLAMP+ or VCLAMP– voltage, the output driver begins to run out of headroom as a result of the clamped supply voltage, shown in Figure 8-12.

The output is unable to swing greater than approximately 500 mV beyond the VCLAMP+ or VCLAMP– voltage (at zero load), helping prevent or reduce damage to the ADC from overvoltage conditions.

The linear operation becomes distorted when the driver load becomes higher than 20 mA, see Figure 8-13.

Figure 8-12 Simplified Schematic of Output Driver Clamping Structure
Note: Be aware that instead of providing an immediate hard-stop voltage limit, the output driver is not clamped until VCLAMP+ or VCLAMP– voltage has been exceeded, and the driver starts to run out of headroom. This configuration prevents distortion of the amplifier output when operating near the VCLAMP+ and VCLAMP– rails. However, the output voltage exceeds VCLAMP+ and VCLAMP– by several hundreds of millivolts before the clamps turn on strongly. When used in conjunction with several tens of ohms of resistance between the amplifier output and ADC input pins (commonly implemented as part of a low-pass filter for proper ADC acquisition), output clamping helps severely diminish any potential damage to the ADC that can otherwise result.
 
Figure 8-13 Output Voltage With Output Clamping Enabled

The VCLAMP+ pin features a fail-safe against power-up sequencing issues between the INA851 and a downstream device. For example, a condition of V(CLAMP+) + 10 V on this pin does not cause damage. Therefore, the ADC supply can safely turn on while the INA851 supply is still off or just beginning to turn on. In this case, the current draw through the VCLAMP+ pin is limited to a safe value of typically 3 mA.