SLLS897E March   2008  – June 2015 ISO1176

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ISODE-Pin
    6. 7.6  Supply Current
    7. 7.7  Electrical Characteristics: Driver
    8. 7.8  Electrical Characteristics: Receiver
    9. 7.9  Power Dissipation Characteristics
    10. 7.10 Switching Characteristics: Driver
    11. 7.11 Switching Characteristics: Receiver
    12. 7.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Insulation and Safety-Related Package Characteristics
      2. 9.3.2 DIN V VDE V 0884-10 Insulation Characteristics
      3. 9.3.3 IEC 60664-1 Ratings Table
      4. 9.3.4 Safety Limiting Values
      5. 9.3.5 Regulatory Information
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Transient Voltages
        2. 10.2.2.2 ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range unless otherwise noted(1)
MIN MAX UNIT
VCC Supply voltage(2) VCC1, VCC2 –0.5 7 V
VO Voltage at any bus I/O pins –9 14 V
VI Voltage input D, DE or RE –0.5 7 V
IO Receiver output current –10 10 mA
TJ Maximum junction temperature 170 °C
Tstg Storage temperature -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) All voltage values except differential I/O bus voltages are with respect to the referenced network ground terminal and are peak voltage values.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Bus pins to 2, 8 ±6000 V
Bus pins to 9, 15 ±16000
All pins ±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Machine model (MM), per ANSI/ESDS5.2-1996, all pins ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Logic-side supply voltage, VCC1 (with respect to GND1) 3.15 5.5 V
Bus-side supply voltage, VCC2 (with respect to GND2) 4.75 5.25
VCM Voltage at either bus I/O terminal A, B –7 12 V
VIH High-level input voltage PV, RE 2 5.5 V
D, DE 0.7 VCC1
VIL Low-level input voltage PV, RE 0 0.8 V
D, DE 0.3 VCC1
VID Differential input voltage A with respect to B –12 12 V
IO Output current Driver –70 70 mA
Receiver –8 8
Input pulse width 10 ns
TA Ambient temperature –40 25 85 °C
TJ Junction temperature 150 °C

7.4 Thermal Information

THERMAL METRIC(1) ISO1176 UNIT
DW [SOIC]
16 PINS
RθJA Junction-to-ambient thermal resistance High-K board 81.4 °C/W
Low-K board 168
RθJC(top) Junction-to-case (top) thermal resistance 41.4 °C/W
RθJB Junction-to-board thermal resistance 46.4 °C/W
ψJT Junction-to-top characterization parameter 13.1 °C/W
ψJB Junction-to-board characterization parameter 45.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ISODE-Pin

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –8 mA VCC2 – 0.8 4.6 V
IOH = –20 μA VCC2 – 0.1 5
VOL Low-level output voltage IOL = 8 mA 0.2 0.4 V
IOL = 20 μA 0 0.1

7.6 Supply Current

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 Logic-side RMS supply current 3 V DE at 0 V 4 6 mA
DE at VCC1, 2 Mbps 5
DE at VCC1, 25 Mbps 6
5.5 V DE at 0 V 7 10
DE at VCC1, 2 Mbps 8
DE at VCC1, 25 Mbps 11
ICC2 Bus-side RMS supply current 5.25 V DE at 0 V 15 18 mA
DE at VCC1, 2 Mbps, 54-Ω load 70
DE at VCC1, 25 Mbps, 54-Ω load 75

7.7 Electrical Characteristics: Driver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Open-circuit differential output voltage |VA – VB|, Figure 8 1.5 VCC2 V
|VOD(SS)| Steady-state differential output voltage magnitude See Figure 9 and Figure 13 2.1 V
Common-mode loading with Vtest from –7 V to 12 V, See Figure 10 2.1
|ΔVOD(SS)| Change in steady-state differential output voltage between logic states RL = 54 Ω, See Figure 11 and Figure 12 –0.2 0.2 V
VOC(SS) Steady-state common-mode output voltage RL = 54 Ω, See Figure 11 and Figure 12 2 3 V
ΔVOC(SS) Change in steady-state common-mode output voltage –0.2 0.2
VOC(PP) Peak-to-peak common-mode output voltage 0.5
VOD(RING) Differential output voltage over- and undershoot See Figure 13 and Figure 17 10% VOD(pp)
VI(HYS) Input voltage hysteresis See Figure 14 150 mV
II Input current D, DE at 0 V or VCC1 –10 10 μA
PV(1) at 0 V or VCC1 120
IO(OFF) Output current with power off VCC ≤ 2.5 V See receiver input current in Electrical Characteristics: Receiver
IOZ High-impedance state output current DE at 0 V
IOS(P) Peak short-circuit output current DE at VCC, See Figure 15 and Figure 16 VOS = –7 V to 12 V –250 250 mA
IOS(SS) Steady-state short-circuit output current VOS = 12 V, D at GND1 135
VOS = –7 V, D at VCC1 –135
COD Differential output capacitance See receiver CIN in Electrical Characteristics: Receiver
CMTI Common-mode transient immunity See Figure 27 25 kV/μs
(1) The PV pin has a 50-kΩ pullup resistor and leakage current depends on supply voltage.

7.8 Electrical Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going differential input voltage threshold SeeFigure 22 IO = –8 mA –80 –10 mV
VIT(–) Negative-going differential input voltage threshold IO = 8 mA –200 –120 mV
Vhys Hysteresis voltage (VIT+ – VIT-) 40 mV
VOH High-level output voltage VCC1 at 3.3 V and VCC2 at 5 V VID = 200 mV,
See Figure 22
IOH = –8 mA VCC1 –0.4 3 V
IOH = –20 μA VCC1 –0.1 3.3
VOL Low-level output voltage VID = –200 mV,
See Figure 22
IOL = 8 mA 0.2 0.4 V
IOL = 20 μA 0 0.1
VOH High-level output voltage VCC1 at 5 V and VCC2 at 5 V VID = 200 mV,
See Figure 22
IOH = –8 mA VCC1 –0.8 4.6 V
IOH = –20 μA VCC1 –0.1 5
VOL Low-level output voltage VID = –200 mV,
See Figure 22
IOL = 8 mA 0.2 0.4 V
IOL = –20 μA 0 0.1
IA, IB Bus pin input current VI = –7 V or 12 V,
Other input = 0 V
VCC = 4.75 V or 5.25 V –160 200 μA
IA(OFF)
IB(OFF)
VCC2 = 0 V
II Receiver enable input current RE = 0 V –50 50 μA
IOZ High-impedance state output current RE = VCC1 –1 1 μA
RID Differential input resistance A, B 48
CID Differential input capacitance Test input signal is a 1.5-MHz sine wave with 1 Vpp amplitude , CD is measured across
A and B
7 10 pF
CMR Common-mode rejection See Figure 26 4 V

7.9 Power Dissipation Characteristics

PARAMETER VALUE UNIT
PD Power Dissipation VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF,
Input a 20 MHz 50% duty-cycle square wave
220 mW

7.10 Switching Characteristics: Driver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH, tpHL Propagation delay time VCC1 at 5 V VCC2 at 5 V See Figure 17 35 ns
tsk(p) Pulse skew (|tpHL – tpLH|) 2 5 ns
tpLH, tpHL Propagation delay time VCC1 at 3.3 V VCC2 at 5 V 40 ns
tsk(p) Pulse skew (|tpHL – tpLH|) 2 5 ns
tr Differential output signal rise time 2 3 7.5 ns
tf Differential output signal fall time 2 3 7.5 ns
tpDE DE to ISODE prop delay See Figure 21 30 ns
tt(MLH), tt(MHL) Output transition skew See Figure 18 1 ns
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active output CL = 50 pF,
RE at 0 V,
See Figure 19 and Figure 20
80 ns
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-to-high-impedance output 80 ns
|tp(AZL) – tp(BZH)|
|tp(AZH) – tp(BZL)|
Enable skew time 0.55 1.5 ns
t(CFB) Time from application of short-circuit to current foldback See Figure 16 0.5 μs
t(TSD) Time from application of short-circuit to thermal shutdown TA = 25°C, See Figure 16 100 μs

7.11 Switching Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH, tpHL Propagation delay time VCC1 at 5 V, VCC2 at 5 V See Figure 23 50 ns
tsk(p) Pulse skew (|tpHL – tpLH|) 2 5 ns
tpLH, tpHL Propagation delay time VCC1 at 3.3 V, VCC2 at 5 V 55 ns
tsk(p) Pulse skew (|tpHL – tpLH|) 2 5 ns
tr Output signal rise time 2 4 ns
tf Output signal fall time 2 4 ns
tpZH Propagation delay time, high-impedance-to-high-level output DE at VCC1,
See Figure 24
13 25 ns
tpHZ Propagation delay time, high-level-to-high-impedance output 13 25 ns
tpZL Propagation delay time, high-impedance-to-low-level output DE at VCC,
See Figure 25
13 25 ns
tpLZ Propagation delay time, low-level-to-high-impedance output 13 25 ns

7.12 Typical Characteristics

ISO1176 dov_load_lls897.gifFigure 1. Differential Output Voltage vs Load Current
ISO1176 doskew_fat_lls897.gifFigure 3. Driver Output Transition Skew vs Free-Air Temperature
ISO1176 dskew_fat_lls897.gifFigure 5. Driver Enable Skew vs Free-Air Temperature
ISO1176 io2_vo_lls897.gifFigure 7. Low-Level Output Voltage vs Low-Level Output Current
ISO1176 icc_sr_lls897.gifFigure 2. RMS Supply Current vs Signaling Rate
ISO1176 drise_fat_lls897.gifFigure 4. Driver Rise and Fall Time vs Free-Air Temperature
ISO1176 io_vo_lls897.gifFigure 6. High-Level Output Voltage vs High-Level Output Current