SLLSFO3 December   2021 ISO6760L

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9.     Electrical Characteristics—5-V Supply
    10. 6.9  Supply Current Characteristics—5-V Supply
    11. 6.10 Electrical Characteristics—3.3-V Supply
    12. 6.11 Supply Current Characteristics—3.3-V Supply
    13. 6.12 Electrical Characteristics—2.5-V Supply 
    14. 6.13 Supply Current Characteristics—2.5-V Supply
    15.     Electrical Characteristics—1.8-V Supply
    16. 6.14 Supply Current Characteristics—1.8-V Supply
    17. 6.15 Switching Characteristics—5-V Supply
    18. 6.16 Switching Characteristics—3.3-V Supply
    19. 6.17 Switching Characteristics—2.5-V Supply
    20. 6.18 Switching Characteristics—1.8-V Supply
    21. 6.19 Insulation Characteristics Curves
    22. 6.20 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 8.3.2 Interlock Capability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10 Insulation Lifetime
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The ISO6760L and ISO6760LN devices are high-performance, six-channel digital isolators with integrated interlock function for applications requiring up to 5000 VRMS isolation ratings per UL 1577. These devices are also certified by VDE, TUV, CSA, and CQC.

The ISO6760L family of devices integrate a series of logic gates to provide hardware interlock functionality for adjacent channels. The interlock feature ensures that each channel, in a channel pairing, will not be enabled at the same time. If both channels in the pairing share the same input logic, the output logic will always be low. The ISO6760L family of devices have all six channels in the same direction and provide high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by TI's double capacitive silicon dioxide (SiO2) insulation barrier.

Used in conjunction with intelligent power modules (IPMs), the interlock feature in these devices help prevent shoot through current between the high side and low side gate driver during turn on and turn off events. Six channels, including three pairings of interlock circuitry, are integrated in a 16-pin SOIC wide-body (DW) package with space savings greater than 50% compared to optocoupler solutions. Through innovative chip design and layout techniques, the electromagnetic compatibility of the ISO6760L devices has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance.

Device Description

Part Number

Package

Body Size

ISO6760L, ISO6760LN SOIC (DW) 10.30 mm × 7.50 mm
Simplified Schematic