SLLS629L January   2006  – October 2015 ISO721 , ISO721M , ISO722 , ISO722M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, 5 V
    6. 7.6  Electrical Characteristics, 5 V, 3.3 V
    7. 7.7  Electrical Characteristics, 3.3 V, 5 V
    8. 7.8  Electrical Characteristics, 3.3 V
    9. 7.9  Power Dissipation
    10. 7.10 Switching Characteristics, 5 V
    11. 7.11 Switching Characteristics, 5 V, 3.3 V
    12. 7.12 Switching Characteristics, 3.3 V, 5 V
    13. 7.13 Switching Characteristics, 3.3 V
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Features Description
      1. 9.3.1 Insulation Characteristics
      2. 9.3.2 IEC 60664-1 Ratings Table
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Package Insulation Characteristics
      5. 9.3.5 Safety Limiting Values
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematic
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design as shown in Figure 23. Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep it symmetrical. Adding a second plane system makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see the Application Note Digital Isolator Design Guide (SLLA284).

12.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics.

12.2 Layout Example

ISO721 ISO721M ISO722 ISO722M layout_sllsei6.gif Figure 23. Recommended Layer Stack