SLLS755P July   2006  – August 2018 ISO7220A , ISO7220B , ISO7220C , ISO7220M , ISO7221A , ISO7221B , ISO7221C , ISO7221M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V VCC1 and V CC2 Supplies
    10. 6.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
    11. 6.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2 Supply
    12. 6.12 Electrical Characteristics—3.3-V VCC1 and VCC2 Supplies
    13. 6.13 Electrical Characteristics—2.8-V VCC1 and VCC2 Supplies
    14. 6.14 Switching Characteristics—5-V VCC1 and VCC2 Supplies
    15. 6.15 Switching Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
    16. 6.16 Switching Characteristics—3.3-V CC1 and 5-V VCC2 Supplies
    17. 6.17 Switching Characteristics—3.3-V VCC1 and VCC2 Supplies
    18. 6.18 Switching Characteristics—2.8-V VCC1 and VCC2 Supplies
    19. 6.19 Insulation Characteristics Curves
    20. 6.20 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

  • Route the high-speed traces on the top layer to avoid the use of vias (and the introduction of the inductances) and allow for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Place a solid ground plane next to the high-speed signal layer to establish controlled impedance for transmission line interconnects and provide an excellent low-inductance path for the return current flow.
  • Place the power plane next to the ground plane to create additional high-frequency bypass capacitance of approximately 100 pF/in2.
  • Route the slower speed control signals on the bottom layer to allow for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. Adding a second plane system to the stack makes the stack mechanically stable and prevents it from warping. The power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide.