SLLS629L January   2006  – October 2015 ISO721 , ISO721M , ISO722 , ISO722M


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, 5 V
    6. 7.6  Electrical Characteristics, 5 V, 3.3 V
    7. 7.7  Electrical Characteristics, 3.3 V, 5 V
    8. 7.8  Electrical Characteristics, 3.3 V
    9. 7.9  Power Dissipation
    10. 7.10 Switching Characteristics, 5 V
    11. 7.11 Switching Characteristics, 5 V, 3.3 V
    12. 7.12 Switching Characteristics, 3.3 V, 5 V
    13. 7.13 Switching Characteristics, 3.3 V
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Features Description
      1. 9.3.1 Insulation Characteristics
      2. 9.3.2 IEC 60664-1 Ratings Table
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Package Insulation Characteristics
      5. 9.3.5 Safety Limiting Values
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematic
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The isolator in the Functional Block Diagram is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, creating a sufficiently high-frequency signal capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing the carrier on to the output multiplexer.

9.2 Functional Block Diagram

ISO721 ISO721M ISO722 ISO722M fbdc_slls868.gif

9.3 Features Description

Insulation characteristics and regulatory information of ISO72x family is provided in this section.

9.3.1 Insulation Characteristics

over recommended operating conditions (unless otherwise noted.)

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(1)
VIORM Maximum working insulation voltage 560 Vpeak
VPR Input to output test voltage After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672 Vpeak
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896 Vpeak
Method b1, VPR = VIORM × 1.875,
100% production test with t = 1 s,
Partial discharge < 5 pC
1050 Vpeak
VIOTM Transient overvoltage t = 60 s 4000 Vpeak
RS Insulation resistance VIO = 500 V at TS > 109 Ω
Pollution degree 2
UL 1577
VISO Isolation voltage VTEST = VISO, t = 60 s (qualification) 3535 / 2500 Vpeak/Vrms
VTEST = 1.2 × VISO, t = 1 s (100% production)(2) 4242 / 3000
(1) Climatic classification 40/125/21
(2) Based on lifetime curve (see the High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report, SLLA197); these devices can withstand 4242 Vpeak / 3000 Vrms for > 10,000 s at 150oC.

9.3.2 IEC 60664-1 Ratings Table

Basic isolation group Material group II
Installation classification Rated mains voltage ≤150 VRMS I-IV
Rated mains voltage ≤300 VRMS I-III

9.3.3 Regulatory Information

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1) Approved according to CSA Component Acceptance Notice 5A and IEC 60950-1 Recognized under UL 1577 Component Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4000 VPK
Maximum Working Voltage, 560 VPK
Maximum Surge Voltage, 4000 VPK
Evaluated to CSA 60950-1-07 and IEC 60950-1 (2nd Ed) with 2000 VRMS Isolation rating for products with working voltages ≤ 125 VRMS for reinforced insulation and ≤ 390 VRMS for basic insulation Single Protection, 2500 VRMS(1)
Certificate number: 40016131 Master contract number: 220991 File number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.

9.3.4 Package Insulation Characteristics

L(101) Minimum air gap (clearance)(1) Shortest terminal-to-terminal distance through air D-8 4 mm
DUB-8 6.1
L(102) Minimum external tracking (creepage)(1) Shortest terminal-to-terminal distance across the package surface D-8 4 mm
DUB-8 6.8
CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 400 V
DTI Distance through insulation Minimum internal gap (internal clearance) 0.008 mm
RIO Isolation resistance Input to output, VIO = 500 V; all pins on each side of the barrier tied together, creating a two-terminal device; TA = 25°C 1012 Ω
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
1011 Ω
CIO Barrier capacitance
VI = 0.4 sin (4 × 106πt) 1 pF
(1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary in the Related Documentation section. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

9.3.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

IS Safety input, output, or supply current θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 100 mA
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 153
TS Maximum case temperature 150 °C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative.

ISO721 ISO721M ISO722 ISO722M safety_v_tc_lls629.gif Figure 16. θJC Thermal Derating Curve per VDE

9.4 Device Functional Modes

Functional modes of ISO72x are shown in Table 1 and Table 2.

Table 1. ISO721 Functional Table

Open H
X PD X Undetermined

Table 2. ISO722 Functional Table

PU PU H L or open H
L L or open L
Open L or open H
PD PU X L or open H
X PD X X Undetermined

9.4.1 Device I/O Schematic

ISO721 ISO721M ISO722 ISO722M equ_cir.gif Figure 17. Equivalent Input and Output Schematic Diagrams