SLLS629L January   2006  – October 2015 ISO721 , ISO721M , ISO722 , ISO722M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, 5 V
    6. 7.6  Electrical Characteristics, 5 V, 3.3 V
    7. 7.7  Electrical Characteristics, 3.3 V, 5 V
    8. 7.8  Electrical Characteristics, 3.3 V
    9. 7.9  Power Dissipation
    10. 7.10 Switching Characteristics, 5 V
    11. 7.11 Switching Characteristics, 5 V, 3.3 V
    12. 7.12 Switching Characteristics, 3.3 V, 5 V
    13. 7.13 Switching Characteristics, 3.3 V
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Features Description
      1. 9.3.1 Insulation Characteristics
      2. 9.3.2 IEC 60664-1 Ratings Table
      3. 9.3.3 Regulatory Information
      4. 9.3.4 Package Insulation Characteristics
      5. 9.3.5 Safety Limiting Values
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematic
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage VCC1, VCC2 –0.5 6 V
VI Input voltage IN, OUT, or EN –0.5 VCC + 0.5(2) V
IO Output current ±15 mA
TJ Maximum junction temperature 170 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum voltage must not exceed 6 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC Supply voltage(1), VCC1, VCC2 3 5.5 V
IOH Output current 4 mA
IOL –4 mA
tui Input pulse duration ISO72x 10 ns
ISO72xM 6.67
1 / tui Signaling Rate ISO72x 0 100 Mbps
ISO72xM 0 150
VIH High-level input voltage (IN, EN) ISO72x 2 5.5 V
VIL Low-level input voltage (IN, EN) 0 0.8 V
VIH High-level input voltage (IN, EN) IOS72xM 0.7 VCC VCC V
VIL Low-level input voltage (IN, EN) 0 0.3 VCC V
TA Ambient temperature –40 25 125 °C
TJ Junction temperature See Thermal Information 150 °C
H External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9 certification 1000 A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.

7.4 Thermal Information

THERMAL METRIC(1) ISO721 ISO72x UNIT
DUB D
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance High-K Board 86.6 114.7 °C/W
Low-K Board N/A 263
RθJC(top) Junction-to-case (top) thermal resistance 70.3 63 °C/W
RθJB Junction-to-board thermal resistance 50.2 54.8 °C/W
ψJT Junction-to-top characterization parameter 34.3 18.9 °C/W
ψJB Junction-to-board characterization parameter 49.8 54.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics, 5 V

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 VCC1 supply current Quiescent VI = VCC or 0 V, no load 0.5 1 mA
25 Mbps 2 4
ICC2 VCC2 supply current ISO722/722M Sleep Mode VI = VCC or 0 V,
No load
EN at VCC 200 μA
Quiescent EN at 0 V or
ISO721/721M
8 12 mA
25 Mbps VI = VCC or 0 V, no load 10 14
VOH High-level output voltage IOH = –4 mA, See Figure 10 VCC – 0.8 4.6 V
IOH = –20 μA, See Figure 10 VCC – 0.1 5
VOL Low-level output voltage IOL = 4 mA, See Figure 10 0.2 0.4 V
IOL = 20 μA, See Figure 10 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current EN, IN at 2 V 10 μA
IIL Low-level input current EN, IN at 0.8 V –10
IOZ High-impedance output current ISO722, ISO722M EN, IN at VCC 1 μA
CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4 × 106πt) 1 pF
CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 14 25 50 kV/μs

7.6 Electrical Characteristics, 5 V, 3.3 V

VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 VCC1 supply current Quiescent VI = VCC or 0 V, no load 0.5 1 mA
25 Mbps 2 4
ICC2 VCC2 supply current ISO722/722M
Sleep mode
VI = VCC or 0 V,
No load
EN at VCC 150 μA
Quiescent EN at 0 V or
ISO721/721M
4 6.5 mA
25 Mbps VI = VCC or 0 V, no load 5 7.5
VOH High-level output voltage IOH = –4 mA, See Figure 10 VCC – 0.4 3 V
IOH = –20 μA, See Figure 10 VCC – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA, See Figure 10 0.2 0.4 V
IOL = 20 μA, See Figure 10 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current EN, IN at 2 V 10 μA
IIL Low-level input current EN, IN at 0.8 V –10 μA
IOZ High-impedance output current ISO722, ISO722M EN, IN at VCC 1 μA
CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4 × 106πt) 1 pF
CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 14 25 40 kV/μs

7.7 Electrical Characteristics, 3.3 V, 5 V

VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 VCC1 supply current Quiescent VI = VCC or 0 V, no load 0.3 0.5 mA
25 Mbps 1 2
ICC2 VCC2 supply current ISO722/722M
Sleep mode
VI = VCC or 0 V,
No load
EN at VCC 200 μA
Quiescent EN at 0 V or
ISO721/721M
8 12 mA
25 Mbps VI = VCC or 0 V, No load 10 14
VOH High-level output voltage IOH = –4 mA, See Figure 10 VCC – 0.8 4.6 V
IOH = –20 μA, See Figure 10 VCC – 0.1 5
VOL Low-level output voltage IOL = 4 mA, See Figure 10 0.2 0.4 V
IOL = 20 μA, See Figure 10 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current EN, IN at 2 V 10 μA
IIL Low-level input current EN, IN at 0.8 V –10 μA
IOZ High-impedance output current ISO722, ISO722M EN, IN at VCC 1 μA
CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4 × 106πt) 1 pF
CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 14 25 40 kV/μs

7.8 Electrical Characteristics, 3.3 V

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC1 VCC1 supply current Quiescent VI = VCC or 0 V, no load 0.3 0.5 mA
25 Mbps 1 2
ICC2 VCC2 supply current ISO722/722M
Sleep Mode
VI = VCC or 0 V,
No load
EN at VCC 150 μA
Quiescent EN at 0 V or
ISO721/721M
4 6.5 mA
25 Mbps VI = VCC or 0 V, no load 5 7.5
VOH High-level output voltage IOH = –4 mA, See Figure 10 VCC – 0.4 3 V
IOH = –20 μA, See Figure 10 VCC – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA, See Figure 10 0.2 0.4 V
IOL = 20 μA, See Figure 10 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current EN, IN at 2 V 10 μA
IIL Low-level input current EN, IN at 0.8 V –10 μA
IOZ High-impedance output current ISO722, ISO722M EN, IN at VCC 1 μA
CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4 × 106πt) 1 pF
CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 14 25 40 kV/μs

7.9 Power Dissipation

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS ISO721
DUB
8 PINS
ISO72x
D
8 PINS
UNIT
PD Power Dissipation ISO72x VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave 159 mW
ISO72xM VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave 195 mW
ISO721 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave 159 mW

7.10 Switching Characteristics, 5 V

VCC1 and VCC2at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay, low-to-high-level output ISO72x EN at 0 V,
See Figure 10
13 17 24 ns
tPHL Propagation delay, high-to-low-level output 13 17 24 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 2 ns
tPLH Propagation delay, low-to-high-level output ISO72xM 8 10 16 ns
tPHL Propagation delay, high-to-low-level output 8 10 16 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 ns
tsk(pp)(1) Part-to-part skew 0 3 ns
tr Output signal rise time EN at 0 V,
See Figure 10
1 ns
tf Output signal fall time 1
tpHZ Sleep-mode propagation delay,
high-level-to-high-mpedance output
ISO722
ISO722M
See Figure 11 6 8 15 ns
tpZH Sleep-mode propagation delay,
high-impedance-to-high-level output
3.5 4 8 μs
tpLZ Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 12 5.5 8 15 ns
tpZL Sleep-mode propagation delay,
high-impedance-to-low-level output
4 5 8 μs
tfs Failsafe output delay time from input power loss See Figure 13 3 μs
tjit(PP) Peak-to-peak eye-pattern jitter ISO72x 100-Mbps NRZ data input, See Figure 15 2 ns
100-Mbps unrestricted bit run length data input, See Figure 15 3
ISO72xM 150-Mbps NRZ data input, See Figure 15 1
150-Mbps unrestricted bit run length data input, See Figure 15 2
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.11 Switching Characteristics, 5 V, 3.3 V

VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay, low-to-high-level output ISO72x EN at 0 V,
See Figure 10
15 19 30 ns
tPHL Propagation delay , high-to-low-level output 15 19 30 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 3 ns
tPLH Propagation delay, low-to-high-level output ISO72xM 10 12 20 ns
tPHL Propagation delay, high-to-low-level output 10 12 20 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 ns
tsk(pp)(1) Part-to-part skew 0 5 ns
tr Output signal rise time EN at 0 V,
See Figure 10
2 ns
tf Output signal fall time 2 ns
tpHZ Sleep-mode propagation delay,
high-level-to-high-mpedance output
ISO722
ISO722M
See Figure 11 7 11 25 ns
tpZH Sleep-mode propagation delay,
high-impedance-to-high-level output
4.5 6 8 μs
tpLZ Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 12 7 13 25 ns
tpZL Sleep-mode propagation delay,
high-impedance-to-low-level output
4.5 6 8 μs
tfs Failsafe output delay time from input power loss See Figure 13 3 μs
tjit(PP) Peak-to-peak eye-pattern jitter ISO72x 100-Mbps NRZ data input, See Figure 15 2 ns
100-Mbps unrestricted bit run length data input, See Figure 15 3
ISO72xM 150-Mbps NRZ data input, See Figure 15 1
150-Mbps unrestricted bit run length data input, See Figure 15 2
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.12 Switching Characteristics, 3.3 V, 5 V

VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay, low-to-high-level output ISO72x EN at 0 V,
See Figure 10
15 17 30 ns
tPHL Propagation delay , high-to-low-level output 15 17 30 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 2 ns
tPLH Propagation delay, low-to-high-level output ISO72xM 10 12 21 ns
tPHL Propagation delay, high-to-low-level output 10 12 21 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 ns
tsk(pp)(1) Part-to-part skew 0 5 ns
tr Output signal rise time EN at 0 V,
See Figure 10
1 ns
tf Output signal fall time 1 ns
tpHZ Sleep-mode propagation delay,
high-level-to-high-mpedance output
ISO722
ISO722M
See Figure 11 7 9 15 ns
tpZH Sleep-mode propagation delay,
high-impedance-to-high-level output
4.5 5 8 μs
tpLZ Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 12 7 9 15 ns
tpZL Sleep-mode propagation delay,
high-impedance-to-low-level output
4.5 5 8 μs
tfs Failsafe output delay time from input power loss See Figure 13 3 μs
tjit(PP) Peak-to-peak eye-pattern jitter ISO72x 100-Mbps NRZ data input, See Figure 15 2 ns
100-Mbps unrestricted bit run length data input, See Figure 15 3
ISO72xM 150-Mbps NRZ data input, See Figure 15 1
150-Mbps unrestricted bit run length data input, See Figure 15 2
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.13 Switching Characteristics, 3.3 V

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay, low-to-high-level output ISO72x EN at 0 V,
See Figure 10
17 20 34 ns
tPHL Propagation delay , high-to-low-level output 17 20 34 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 3 ns
tPLH Propagation delay, low-to-high-level output ISO72xM 10 12 25 ns
tPHL Propagation delay, high-to-low-level output 10 12 25 ns
tsk(p) Pulse skew |tPHL – tPLH| 0.5 1 ns
tsk(pp)(1) Part-to-part skew 0 5 ns
tr Output signal rise time EN at 0 V,
See Figure 10
2 ns
tf Output signal fall time 2
tpHZ Sleep-mode propagation delay,
high-level-to-high-mpedance output
ISO722
ISO722M
See Figure 11 7 13 25 ns
tpZH Sleep-mode propagation delay,
high-impedance-to-high-level output
5 6 8 µs
tpLZ Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 12 7 13 25 ns
tpZL Sleep-mode propagation delay,
high-impedance-to-low-level output
5 6 8 μs
tfs Failsafe output delay time from input power loss See Figure 13 3 μs
tjit(PP) Peak-to-peak eye-pattern jitter ISO72x 100-Mbps NRZ data input, See Figure 15 2 ns
100-Mbps unrestricted bit run length data input, See Figure 15 3
ISO72xM 150-Mbps NRZ data input, See Figure 15 1
150-Mbps unrestricted bit run length data input, See Figure 15 2
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.14 Typical Characteristics

ISO721 ISO721M ISO722 ISO722M icc_33v_sr_lls629.gif
Figure 1. RMS Supply Current vs Signaling Rate
ISO721 ISO721M ISO722 ISO722M pgdl_33v_ta_lls629.gif
Figure 3. Propagation Delay vs Free-Air Temperature
ISO721 ISO721M ISO722 ISO722M vi_iso_ta_lls629.gif
Figure 5. ISO72x Input Threshold Voltage vs Free-Air Temperature
ISO721 ISO721M ISO722 ISO722M vcc1_v_ta_lls629.gif
Figure 7. VCC1 Failsafe Threshold Voltage vs Free-Air Temperature
ISO721 ISO721M ISO722 ISO722M iol_v_vol_lls629.gif
Figure 9. Low-Level Output Current vs Low-Level Output Voltage
ISO721 ISO721M ISO722 ISO722M icc_5v_sr_lls629.gif
Figure 2. RMS Supply Current vs Signaling Rate
ISO721 ISO721M ISO722 ISO722M pgdl_5v_ta_lls629.gif
Figure 4. Propagation Delay vs Free-Air Temperature
ISO721 ISO721M ISO722 ISO722M vi_isom_ta_lls629.gif
Figure 6. ISO72xM Input Threshold Voltage vs Free-Air Temperature
ISO721 ISO721M ISO722 ISO722M ioh_v_voh_lls629.gif
Figure 8. High-Level Output Current vs High-Level Output Voltage