SLLS868T September   2007  – April 2017 ISO7240C , ISO7240CF , ISO7240M , ISO7241C , ISO7241M , ISO7242C , ISO7242M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
    10. 7.10 Supply Current Characteristics: VCC1 and VCC2 at 5-V Operation
    11. 7.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 7.12 Supply Current Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    13. 7.13 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    14. 7.14 Supply Current Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 7.15 Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
    16. 7.16 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V Operation
    17. 7.17 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
    18. 7.18 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    19. 7.19 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
    20. 7.20 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    21. 7.21 Insulation Characteristics Curves
    22. 7.22 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Isolated Data Acquisition System for Process Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Isolated SPI for an Analog Input Module with 16 Inputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Isolated RS-232 Interface
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configurations and Functions

ISO7240CF DW Package
16-Pin SOIC
Top View
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M po_DW_iso7240cf_slls868.gif
ISO7240C and ISO7240M DW Package
16-Pin SOIC
Top View
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M po_DW_iso7240_slls868.gif
ISO7241C and ISO7241M DW Package
16-Pin SOIC
Top View
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M po_DW_iso7241_slls868.gif
ISO7242C and ISO7242M DW Package
16-Pin SOIC
Top View
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M po_DW_iso7242_slls868.gif

Pin Functions

PIN I/O DESCRIPTION3
NAME NO.
ISO7240CF ISO7240C
ISO7240M		 ISO7241C
ISO7241M		 ISO7242C
ISO7242M
CTRL 10 — — — I Failsafe output control. Output state is determined by CTRL pin when DISABLE is high or VCC1 is powered down. Output is high when CTRL is high or open and low when CTRL is low.
DISABLE 7 — — — I Input disable. All input pins are disabled when DISABLE is high and enabled when DISABLE is low or open.
EN — 10 — — I Output enable. All output pins are enabled when EN is high or open and disabled when EN is low.
EN1 — — 7 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and disabled when EN1 is low.
EN2 — — 10 10 I Output enable 2. Output pins on side-2 are enabled when EN2 is high or open and disabled when EN2 is low.
GND1 2, 8 2, 8 2, 8 2, 8 — Ground connection for VCC1
GND2 9, 15 9, 15 9, 15 9, 15 — Ground connection for VCC2
INA 3 3 3 3 I Input, channel A
INB 4 4 4 4 I Input, channel B
INC 5 5 5 12 I Input, channel C
IND 6 6 11 11 I Input, channel D
NC — 7 — — — No Connect pins are floating with no internal connection
OUTA 14 14 14 14 O Output, channel A
OUTB 13 13 13 13 O Output, channel B
OUTC 12 12 12 5 O Output, channel C
OUTD 11 11 6 6 O Output, channel D
VCC1 1 1 1 1 — Power supply, VCC1
VCC2 16 16 16 16 — Power supply, VCC2