SLLSFK1C september   2021  – april 2022 ISOW7740 , ISOW7741 , ISOW7742 , ISOW7743 , ISOW7744

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics - Power Converter
    10. 7.10 Supply Current Characteristics - Power Converter
    11. 7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
    12. 7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
    13. 7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    14. 7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
    15. 7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    16. 7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
    17. 7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    18. 7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
    19. 7.19 Switching Characteristics - 5-V Supply
    20. 7.20 Switching Characteristics - 3.3-V Supply
    21. 7.21 Switching Characteristics - 2.5-V Supply
    22. 7.22 Switching Characteristics - 1.8-V Supply
    23. 7.23 Insulation Characteristics Curves
    24. 7.24 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Power Isolation
      2. 9.1.2 Signal Isolation
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Power-Up and Power-Down Behavior
      3. 9.3.3 Protection Features
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
      4. 10.2.4 Insulation Lifetime
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Power-Up and Power-Down Behavior

The ISOW774x device has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be present for the device to work. If either of them is below its UVLO, both the signal path and the power converter are disabled.

When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO or VDD voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the normal state defined by the respective input channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.

When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to discharge to zero.