SWRS228A September   2019  – January 2022 IWR1843

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Peripheral Mode I/O Timings
          1. 8.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 8.10.6  Controller Area Network Interface (DCAN)
        1. 8.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 8.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 8.10.8  Serial Communication Interface (SCI)
        1. 8.10.8.1 SCI Timing Requirements
      9. 8.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.9.1 I2C Timing Requirements (1)
      10. 8.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.10.1 QSPI Timing Conditions
        2. 8.10.10.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.10.3 QSPI Switching Characteristics
      11. 8.10.11 ETM Trace Interface
        1. 8.10.11.1 ETMTRACE Timing Conditions
        2. 8.10.11.2 ETM TRACE Switching Characteristics
      12. 8.10.12 Data Modification Module (DMM)
        1. 8.10.12.1 DMM Timing Requirements
      13. 8.10.13 JTAG Interface
        1. 8.10.13.1 JTAG Timing Conditions
        2. 8.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 9.3.5 DSP Subsystem Memory Map
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from September 18, 2019 to January 15, 2022 (from Revision * (September 2019) to Revision A (January 2022))

  • Global: Datasheet updated to reflect Functional Safety-Compliance status of the mmWave device; Relevant Certification Collateral and details added Go
  • Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminologyGo
  • (Features) : Mentioned the specific operating temperature range for the mmWave SensorGo
  • (Device Information) : Functional Safety-Compliant OPNs for IWR1843 device updatedGo
  • Updated/Changed Functional Block Diagram for inclusive terminologyGo
  • (Device Comparison): Added a table-note to reflect Functional Safety-Compliance status of the device and LVDS Interface; Updated Product status for IWR6843 and IWR6843AOP devices from "AI" to "PD"Go
  • Updated Top Right Quadrant image to match complete Pin DiagramGo
  • Section 7.2 (Signal Descriptions): Added NOTE on digital IO pinsGo
  • (Signal Descriptions): Added a NOTE on the GPIO state during power supply rampGo
  • (Signal Descriptions): Added a NOTE on the GPIO state during power supply rampGo
  • (Signal Descriptions - Digital) : Added ADC_VALID, CHIRP_END, CHIRP_START, and FRAME_START SIGNAL NAME rowsGo
  • (Signal Description - Digital): Added missing DESCRIPTIONS to the EPWMxSYNC SIGNAL NAME rowsGo
  • (Signal Description - Digital) : Deleted BALL NO. "D14" from the EPWM1SYNCI rowGo
  • Updated/Changed CLKP and CLKM descriptions in Signal Descriptions Go
  • Updated/Changed CLKP and CLKM descriptions in Signal Descriptions Go
  • Removed R14 from Power supply VIOINGo
  • Added pin R15 to Power supply VSSGo
  • (Signal Descriptions) :Updated/Changed CLKP and CLKM descriptionsGo
  • (Pin Attributes (ABL0161 Package): Added the ADC_VALID, CHIRP_END, CHIRP_START, and FRAME_START signal names, modes, and type to each applicable BALL NUMBER.Go
  • (Pin Attributes (ABL0161 Package): Corrected BALL NUMBER "C13" to "E15" and MODE 0 "SPIA_cs_n" (duplicate) to "GPIO_30" SIGNAL NAME.Go
  • (Pin Attributes (ABL0161 Package): Corrected BALL NUMBER C13 MODE 0 "SPIA_cs_n" (duplicate) to "GPIO_30" SIGNAL NAME.Go
  • (Pin Attributes (ABL0161 Package): Corrected BALL NUMBER F14 MODE 1 "SPIB-clk1" to "SPIB-clk" SIGNAL NAME.Go
  • (Pin Attributes (ABL0161 Package): Removed MODE 1 "RESERVED" from BALL NUMBER N14.Go
  • Updated/Changed N14 from GPIO48 to DMM_SYNCGo
  • Updated/Changed N14 from GPIO48 to DMM_SYNCGo
  • Added two register tables after Pin AttributesGo
  • (PAD IO Control Registers): Updated/Changed table.Go
  • (Pin Attributes): Updated/Changed table to remove unsupported mux modes and deleted unsupported CAN signal names.Go
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (Maximum Current Ratings at Power Terminals): Updated the table-notes section to reflect typical supply voltage level conditions.Go
  • Updated Average Power Consumption at Power TerminalsGo
  • (Average Power Consumption at Power Terminals): Updated/Changed the typical average power numbersGo
  • (RF Specifications) : Added lead-in paragraph and "Noise Figure, In-band P1dB vs Receiver Gain" image.Go
  • Section 8.9 (Thermal Resistance Characteristics for FCBGA Package [ABL0161]): Updated/Changed all thermal resistance values for ABL package and changed associated Air flow footnote.Go
  • (Clock Specifications): Updated/Changed Table 8-5 to reflect correct device operating temperature range.Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • Added footnote to DSS_L3RAM Shared memory in Master Subsystem, Cortex-R4F Memory Map Go
  • Added a footnote for L3-Shared memory in DSP C674x Memory Map Go
  • Updated/Changed ADC Channels (Service) for User Application text from "...for ADC channel mapped to B12..." to "...for ADC channel mapped to C14..."Go
  • Updated/Changed ADC Channels (Service) for User Application text from "...for ADC channel mapped to B12..." to "...for ADC channel mapped to C14..."Go
  • Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6"Go
  • ADC Path: Updated/Changed the incomplete footnote.Go
  • Section 9.4.1.1 (GP-ADC Parameter): Added parameter tableGo
  • (Monitoring and Diagnostic Mechanisms):Updated/modfied Monitoring and Diagnostics mechanisms for Functional Safety-Compliant IWR1843 deviceGo
  • Section 11.2 (Reference Schematic): Updated/Changed the VBGAP decoupling capacitor value from "0.22 uF" to "47 nF".Go
  • Removed Low-Noise LDO Circuitry imageGo
  • (Reference Schematics) : Added weblinks to device EVM documentation collateral Go
  • (Device Nomenclature):Updated/changed Device Nomenclature Go