SWRS228A September   2019  – January 2022 IWR1843


  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. Peripheral Description
        2. MibSPI Transmit and Receive RAM Organization
          1. SPI Timing Conditions
          2. SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. SPI Peripheral Mode I/O Timings
          1. SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. Typical Interface Protocol Diagram (Peripheral Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 8.10.6  Controller Area Network Interface (DCAN)
        1. Dynamic Characteristics for the DCANx TX and RX Pins
      7. 8.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Dynamic Characteristics for the CANx TX and RX Pins
      8. 8.10.8  Serial Communication Interface (SCI)
        1. SCI Timing Requirements
      9. 8.10.9  Inter-Integrated Circuit Interface (I2C)
        1. I2C Timing Requirements (1)
      10. 8.10.10 Quad Serial Peripheral Interface (QSPI)
        1. QSPI Timing Conditions
        2. Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. QSPI Switching Characteristics
      11. 8.10.11 ETM Trace Interface
        1. ETMTRACE Timing Conditions
        2. ETM TRACE Switching Characteristics
      12. 8.10.12 Data Modification Module (DMM)
        1. DMM Timing Requirements
      13. 8.10.13 JTAG Interface
        1. JTAG Timing Conditions
        2. Timing Requirements for IEEE 1149.1 JTAG
        3. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. Clock Subsystem
        2. Transmit Subsystem
        3. Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 9.3.5 DSP Subsystem Memory Map
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Main Subsystem Cortex-R4F Memory Map

Table 9-1 shows the main subsystem, Cortex-R4F memory map.


There are separate Cortex-R4F addresses and DMA MSS addresses for the main subsystem. See the Technical Reference Manual for a complete list.

Table 9-1 Main Subsystem, Cortex-R4F Memory Map
CPU Tightly-Coupled Memories
TCMA ROM0x0000_00000x0001_FFFF128 KiBProgram ROM
TCM RAM-A0x0020_00000x0023_FFFF (or 0x0027_FFFF)512 KiB256/512KB based on variant
TCM RAM-B0x0800_00000x0802_FFFF192 KBData RAM
S/W Scratch Pad Memory
SW_ Buffer0x0C20_00000x0C20_1FFF8 KBS/W Scratchpad memory
System Peripherals
Mail Box
0xF060_10000xF060_17FF2 KBRADARSS to MSS mailbox memory space
0xF060_20000xF060_27FFMSS to RADARSS mailbox memory space
0xF060_80000xF060_80FF188 BMSS to RADARSS mailbox Configuration registers
0xF060_80600xF060_86FFRADARSS to MSS mailbox Configuration registers
Mail Box
0xF060_40000xF060_47FF2 KBDSPSS to MSS mailbox memory space
0xF060_50000xF060_57FFMSS to DSPSS mailbox memory space
0xF060_84000xF060_84FF188 BMSS to DSPSS mailbox Configuration registers
0xF060_83000xF060_83FFDSPSS to MSS mailbox Configuration registers
Mail Box
0xF060_60000xF060_67FF2 KBRADARSS to DSPSS mailbox memory space
0xF060_70000xF060_7FFFDSPSS to RADARSS mailbox memory space
0xF060_82000xF060_82FF188 BRADARSS to DSPSS mailbox Configuration registers
0xF060_81000xF060_81FFDSPSS to RADARSS mailbox Configuration registers
PRCM and Control Module0xFFFF_E1000xFFFF_E2FF756 BTOP Level Reset, Clock management registers
0xFFFF_FF000xFFFF_FFFF256 BMSS Reset, Clock management registers
0xFFFF_EA000xFFFF_EBFF512 KBIO Mux module registers
0xFFFF_F8000xFFFF_FBFF352 BGeneral-purpose control registers
GIO0xFFF7_BC000xFFF7_BDFF180 BGIO module configuration registers
DMA-10xFFFF_F0000xFFFF_F3FF1 KBDMA-1 module configuration registers
DMA-20xFCFF_F8000xFCFF_FBFF1 KBDMA-2 module configuration registers
DMM-10xFCFF_F7000xFCFF_F7FF472 BDMM-1 module configuration registers
DMM-20xFCFF_F6000xFCFF_F6FF472 BDMM-2 module configuration registers
VIM0xFFFF_FD000xFFFF_FEFF512 BVIM module configuration registers
RTI-A/WD0xFFFF_FC000xFFFF_FCFF192 BRTI-A module configuration registers
RTI-B0xFFFF_EE000xFFFF_EEFF192 BRTI-B module configuration registers
Serial Interfaces and Connectivity
QSPI0xC000_00000xC07F_FFFF8 MBQSPI –flash memory space
0xC080_00000xC0FF_FFFF116 BQSPI module configuration registers
MIBSPI-A0xFFF7_F4000xFFF7_F5FF512 BMIBSPI-A module configuration registers
MIBSPI-B0xFFF7_F6000xFFF7_F7FF512 BMIBSPI-B module configuration registers
SCI-A0xFFF7_E5000xFFF7_E5FF148 BSCI-A module configuration registers
SCI-B0xFFF7_E7000xFFF7_E7FF148 BSCI-B module configuration registers
CAN0xFFF7_DC000xFFF7_DDFF512 BCAN module configuration registers
CAN_FD(MCAN)0xFFF7_C8000xFFF7_CFFF768 BCAN-FD module configuration registers
0xFFF7_A0000xFFF7_A1FF452 BMCAN ECC module registers
I2C0xFFF7_D4000xFFF7_D4FF112 BI2C module configuration registers
PCR-10xFFF7_80000xFFF7_87FF1 KiBPCR-1 interconnect configuration port
PCR-20xFCFF_10000xFCFF_17FF1 KiBPCR-2 interconnect configuration port
Safety Modules
CRC0xFE00_00000xFEFF_FFFF16 KiBCRC module configuration registers
PBIST0xFFFF_E4000xFFFF_E5FF464 BPBIST module configuration registers
STC0xFFFF_E6000xFFFF_E7FF284 BSTC module configuration registers
DCC-A0xFFFF_EC000xFFFF_ECFF44 BDCC-A module configuration registers
DCC-B0xFFFF_F4000xFFFF_F4FF44 BDCC-B module configuration registers
ESM0xFFFF_F5000xFFFF_F5FF156 BESM module configuration registers
CCMR40xFFFF_F6000xFFFF_F6FF136 BCCMR4 module configuration registers
Security Modules
Crypto0xFD00_00000XFDFF_FFFF3 KiBCrypto module configuration registers
Other Subsystems
DSS_TPTC00x5000 00000x5000 0317792 BTPTC0 module configuration space
DSS_REG0x5000 04000x5000 075F864 BDSPSS control module registers
DSS_TPTC10x5000 08000x5000 0B17792 BTPTC1 module configuration space
DSS_REG20x5000 0C000x5000 0EA3676 BDSPSS control module registers
DSS_TPCC00x5001 00000x5001 3FFF16 KBTPCC0 module configuration space
DSS_RTIA/WDT0x5002 00000x5002 00BF192 BDSS_RTIA/WDT configuration space
DSS_SCI0x5003 00000x5003 0093148 BSCI memory space
DSS_STC0x5004 00000x5004 011B284 BSTC module configuration space
DSS_CBUFF0x5007 00000x5007 0233564 BCommon Buffer module configuration registers
DSS_TPTC20x5009 00000x5009 0317792 BTPTC2 module configuration space
DSS_TPTC30x5009 04000x5009 0717792 BTPTC3 module configuration space
DSS_TPCC10x500A 00000x500A 3FFF16 KBTPCC1 module configuration space
DSS_ESM0x500D 00000x500D 005B92 BESM module configuration registers
DSS_RTIB0x500F 00000x500F 00BF192 BRTI-B module configuration registers
DSS_L3RAM Shared memory0x5100 00000x511F FFFF2 MB(1)L3 shared memory space
DSS_ADCBUF Buffer0x5200 00000x5200 7FFF32 KBADC buffer memory space
DSS_CBUFF_FIFO0x5202 00000x5202 3FFF16 KBCommon buffer FIFO space
DSS_HSRAM10x5208 00000x5208 7FFF32 KBHandshake memory space
DSS_DSP_L2_UMAP10x577E 00000x577F FFFF128 KBL2 RAM space
DSS_DSP_L2_UMAP00x5780 00000x5781 FFFF128 KBL2 RAM space
DSS_DSP_L1P0x57E0 00000x57E0 7FFF32 KBL1 program memory space
DSS_DSP_L1D0x57F0 00000x57F0 7FFF32 KBL1 data memory space
Peripheral Memories (System and Nonsystem)
CAN RAM0xFF1E_00000xFF1F_FFFF128 KBCAN RAM memory space
CAN-FD RAM0xFF50_00000xFF51_FFFF68 KBCAN-FD RAM memory space
DMA1 RAM0xFFF8_00000xFFF8_0FFF4 KBDMA1 RAM memory space
DMA2 RAM0xFCF8 10000xFCF8_0FFF4 KBDMA2 RAM memory space
VIM RAM0xFFF8_20000xFFF8_2FFF2 KBVIM RAM memory space
MIBSPIB-TX RAM0xFF0C_00000xFF0C_01FF0.5 KBMIBSPIB-TX RAM memory space
MIBSPIB-RX RAM0xFF0C_02000xFF0C_03FF0.5 KBMIBSPIB-RX RAM memory space
MIBSPIA-TX RAM0xFF0E_00000xFF0E_01FF0.5 KBMIBSPIA-TX RAM memory space
MIBSPIA- RX RAM0xFF0E_02000xFF0E_03FF0.5 KBMIBSPIA- RX RAM memory space
Debug Modules
Debug subsystem0xFFA0_00000xFFAF_FFFF244 KBDebug subsystem memory space and registers
768 KB memory within 2 MB memory space