SNOS412O February 2000 – June 2020 LM1117
Some layout guidelines must be followed to ensure proper regulation of the output voltage with minimum noise. Traces carrying the load current must be wide to reduce the amount of parasitic trace inductance and the feedback loop from VOUT to ADJ must be kept as short as possible. To improve PSRR, a bypass capacitor can be placed at the ADJ pin and must be located as close as possible to the IC. In cases when VIN shorts to ground, an external diode must be placed from VOUT to VIN to divert the surge current from the output capacitor and protect the IC. The diode must be placed close to the corresponding IC pins to increase their effectiveness.