SNVS585M September   2008  – October 2020 LM22678 , LM22678-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings: LM22678
    3. 6.3 Handling Ratings: LM22678-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precision Enable and UVLO
      2. 7.3.2 Soft Start
      3. 7.3.3 Bootstrap Supply
      4. 7.3.4 Internal Loop Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Current Limit
      4. 7.4.4 Thermal Protection
      5. 7.4.5 Duty-Cycle Limits
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Voltage Divider Selection
      2. 8.1.2 Power Diode
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Buck Regulator Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components
            1. Inductor
          2. Input Capacitor
          3. Output Capacitor
          4. Bootstrap Capacitor
        3. Application Curves
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Board layout is critical for the proper operation of switching power supplies. First, the ground plane area must be sufficient for thermal dissipation purposes. Second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such cases, the rapid increase of input current combined with the parasitic trace inductance generates unwanted L di/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise.

The most important layout rule is to keep the ac current loops as small as possible. Figure 9-1 shows the current flow in a buck converter. The top schematic shows a dotted line which represents the current flow during the FET switch on-state. The middle schematic shows the current flow during the FET switch off-state.

The bottom schematic shows the currents referred to as ac currents. These ac currents are the most critical because they are changing in a very short time period. The dotted lines of the bottom schematic are the traces to keep as short and wide as possible. This will also yield a small loop area reducing the loop inductance. To avoid functional problems due to layout, review the PCB layout example. Best results are achieved if the placement of the LM22678 device, the bypass capacitor, the Schottky diode, RFBB, RFBT, and the inductor are placed as shown in Figure 9-1. In the layout shown, R1 = RFBB and R2 = RFBT. It is also recommended to use 2 oz copper boards or heavier to help thermal dissipation and to reduce the parasitic inductances of board traces. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054) for more information.

GUID-C178D946-A1FF-4479-89C0-5104B248BEF8-low.gifFigure 9-1 Current Flow in a Buck Application