SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Compensation Components

Choose compensation components for a stable control loop using the procedure outlined as follows:

  1. Based on a specified loop gain crossover frequency, fC, of 55kHz, use Equation 44 to calculate RCOMP, assuming an effective output capacitance of 100µF. Choose a standard value for RCOMP of 7.87kΩ.
    Equation 44. R C O M P = 2 π × f C × V O U T V R E F × R S × G C S g m × C O U T = 2 π × 55 k H z × 5 V 0.8 V × 4 m × 10 1100 μ S × 100 μ F = 7.85 k
  2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the load pole. Use Equation 45 to calculate the CCOMP value. Choose a standard value for CCOMP of 3.3nF.
    Equation 45. C C O M P = 10 2 π × f C × R C O M P = 10 2 π × 55 k H z × 7.87 k = 3.68 n F

    Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout (when the input voltage is less than the output voltage setpoint and VCOMP is railed high).

  3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP using Equation 46. CBW is the bandwidth-limiting capacitance of the error amplifier. CHF can not be significant enough to be necessary in some designs. For this design, select a standard value for CHF of 10pF.
    Equation 46. C H F = 1 2 π × f E S R × R C O M P - C B W = 1 2 π × 500 k H z × 7.87 k - 31 = 9.44 p F
Note: Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from operation in dropout.
Note: For technical designs, industry trends, and insights for designing and managing power supplies, see also TI's technical articles.