SNVSC03A June   2021  – February 2023 LM25148-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings 
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Dual Random Spread Spectrum (DRSS)
      7. 8.3.7  Soft Start
      8. 8.3.8  Output Voltage Setpoint (FB)
      9. 8.3.9  Minimum Controllable On Time
      10. 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.12.1 Shunt Current Sensing
        2. 8.3.12.2 Inductor DCR Current Sensing
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
      15. 8.3.15 Output Configurations (CNFG)
      16. 8.3.16 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Frequency Set Resistor
          7. 9.2.1.2.7 Feedback Resistors
          8. 9.2.1.2.8 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Example

#SNVSB291583 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and Q2, in SON 5-mm × 6-mm case size. The power stage is surrounded by a GND pad geometry to connect an EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.

The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C15 through C18. The currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance. #SNVSB061585 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in #SNVSB291584, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of Q2.

Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of Q1. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic loop inductance.

Figure 9-36 PCB Top Layer – High Density, Single-sided Design

Additional guidelines to improve noise immunity and reduce EMI are as follows:

  • Make the ground connections to the LM25148 controller as shown in #SNVSB291583. Create a power ground directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane for AGND and power ground plane for PGND must be connected at a single point directly under the IC – at the die attach pad (DAP).
  • Connect the MOSFETs (switch node) directly to the inductor terminal with short copper connections (without vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI signature.
  • Place the EMI filter components on the bottom side of the PCB so that they are shielded from the power stage components on the top side.
Figure 9-37 Layer 2 Full Ground Plane Directly Under the Power Components
GUID-6EA1ECA0-53B4-4F7E-8814-540DEE36027B-low.gifFigure 9-38 PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing (1)