SNVSB28 December 2017 LM25575-Q1

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information

- PWP|16

- PWP|16

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM25575-Q1 is as follows:

Equation 12. DC Gain_{(MOD)} = G_{m(MOD)} × R_{LOAD} = 1 × R_{LOAD}

The dominant low frequency pole of the modulator is determined by the load resistance (R_{LOAD},) and output capacitance (C_{OUT}). The corner frequency of this pole is as follows:

Equation 13. f_{p(MOD)} = 1 / (2π R_{LOAD} C_{OUT})

For R_{LOAD} = 5 Ω and C_{OUT} = 130 µF then f_{p(MOD)} = 245 Hz

DC Gain_{(MOD)} = 1 × 5 = 14 dB

For the design example of *Functional Block Diagram* the following modulator gain vs. frequency characteristic was measured as shown in Figure 11.

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a zero at f_{Z} = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. The compensation network zero (f_{Z}) should be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2 kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was selected for 0.01 µF and R4 was selected for 49.9 kΩ. These values configure the compensation network zero at 320 Hz. The error amp gain at frequencies greater than f_{Z} is: R4 and R5, which is approximately 10 (20 dB).

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C6 is: f_{p2} = fz × C5 / C6.