SNVS124E November   1999  – February 2020 LM2596

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics – 3.3-V Version
    6. 7.6  Electrical Characteristics – 5-V Version
    7. 7.7  Electrical Characteristics – 12-V Version
    8. 7.8  Electrical Characteristics – Adjustable Voltage Version
    9. 7.9  Electrical Characteristics – All Output Voltage Versions
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Delayed Start-Up
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Inverting Regulator
      4. 8.3.4 Inverting Regulator Shutdown Methods
    4. 8.4 Device Functional Modes
      1. 8.4.1 Discontinuous Mode Operation
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor (CIN)
      2. 9.1.2 Feedforward Capacitor (CFF)
      3. 9.1.3 Output Capacitor (COUT)
      4. 9.1.4 Catch Diode
      5. 9.1.5 Inductor Selection
      6. 9.1.6 Output Voltage Ripple and Transients
      7. 9.1.7 Open-Core Inductors
    2. 9.2 Typical Applications
      1. 9.2.1 LM2596 Fixed Output Series Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH Tools
          2. 9.2.1.2.2 Inductor Selection (L1)
          3. 9.2.1.2.3 Output Capacitor Selection (COUT)
          4. 9.2.1.2.4 Catch Diode Selection (D1)
          5. 9.2.1.2.5 Input Capacitor (CIN)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 LM2596 Adjustable Output Series Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming Output Voltage
          2. 9.2.2.2.2 Inductor Selection (L1)
          3. 9.2.2.2.3 Output Capacitor Selection (COUT)
          4. 9.2.2.2.4 Feedforward Capacitor (CFF)
          5. 9.2.2.2.5 Catch Diode Selection (D1)
          6. 9.2.2.2.6 Input Capacitor (CIN)
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Custom Design with WEBENCH Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NDH|5
  • NEB|5
  • KTT|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics – All Output Voltage Versions

Specifications are for TJ = 25°C, ILOAD = 500 mA, VIN = 12 V for the 3.3-V, 5-V, and adjustable version, and VIN = 24 V for the 12-V version (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
DEVICE PARAMETERS
Ib Feedback bias current Adjustable version only,
VFB = 1.3 V
TJ = 25°C 10 50 nA
–40°C ≤ TJ ≤ 125°C 100
fO Oscillator frequency(3) TJ = 25°C 127 150 173 kHz
–40°C ≤ TJ ≤ 125°C 110 173
VSAT Saturation voltage(4)(5) IOUT = 3 A TJ = 25°C 1.16 1.4 V
–40°C ≤ TJ ≤ 125°C 1.5
DC Max duty cycle (ON)(5) 100%
Min duty cycle (OFF)(6) 0%
ICL Current limit(4)(5) Peak current TJ = 25°C 3.6 4.5 6.9 A
–40°C ≤ TJ ≤ 125°C 3.4 7.5
IL Output leakage current(4)(6) Output = 0 V, VIN = 40 V 50 μA
Output = –1 V 2 30 mA
IQ Operating quiescent current(6) See (6) 5 10 mA
ISTBY Current standby quiescent ON/OFF pin = 5 V (OFF)(7) TJ = 25°C 80 200 μA
–40°C ≤ TJ ≤ 125°C 250 μA
SHUTDOWN/SOFT-START CONTROL (see Figure 35 for test circuit)
VIH ON/OFF pin logic input threshold voltage Low (regulator ON) TJ = 25°C 1.3 V
–40°C ≤ TJ ≤ 125°C 0.6
VIL High (regulator OFF) TJ = 25°C 1.3 V
–40°C ≤ TJ ≤ 125°C 2
IH ON/OFF pin input current VLOGIC = 2.5 V (regulator OFF) 5 15 μA
IL VLOGIC = 0.5 V (regulator ON) 0.02 5 μA
All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
The switching frequency is reduced when the second stage current limit is activated. The amount of reduction is determined by the severity of current overload.
No diode, inductor, or capacitor connected to output pin.
Feedback pin removed from output and connected to 0 V to force the output transistor switch ON.
Feedback pin removed from output and connected to 12 V for the 3.3-V, 5-V, and the adjustable versions, and 15 V for the 12-V version, to force the output transistor switch OFF.
VIN = 40 V.