SNVS124D November   1999  – May 2016 LM2596

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - 3.3-V Version
    6. 7.6  Electrical Characteristics - 5-V Version
    7. 7.7  Electrical Characteristics - 12-V Version
    8. 7.8  Electrical Characteristics - Adjustable Voltage Version
    9. 7.9  Electrical Characteristics - All Output Voltage Versions
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Delayed Start-Up
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Inverting Regulator
      4. 8.3.4 Inverting Regulator Shutdown Methods
    4. 8.4 Device Functional Modes
      1. 8.4.1 Discontinuous Mode Operation
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor (CIN)
      2. 9.1.2 Feedforward Capacitor (CFF)
      3. 9.1.3 Output Capacitor (COUT)
      4. 9.1.4 Catch Diode
      5. 9.1.5 Inductor Selection
      6. 9.1.6 Output Voltage Ripple and Transients
      7. 9.1.7 Open-Core Inductors
    2. 9.2 Typical Applications
      1. 9.2.1 LM2596 Fixed Output Series Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH Tools
          2. 9.2.1.2.2 Inductor Selection (L1)
          3. 9.2.1.2.3 Output Capacitor Selection (COUT)
          4. 9.2.1.2.4 Catch Diode Selection (D1)
          5. 9.2.1.2.5 Input Capacitor (CIN)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 LM2596 Adjustable Output Series Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming Output Voltage
          2. 9.2.2.2.2 Inductor Selection (L1)
          3. 9.2.2.2.3 Output Capacitor Selection (COUT)
          4. 9.2.2.2.4 Feedforward Capacitor (CFF)
          5. 9.2.2.2.5 Catch Diode Selection (D1)
          6. 9.2.2.2.6 Input Capacitor (CIN)
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Custom Design with WEBENCH Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NDH|5
  • NEB|5
  • KTT|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Maximum supply voltage (VIN) 45 V
SD/SS pin input voltage(3) 6 V
Delay pin voltage(3) 1.5 V
Flag pin voltage –0.3 45 V
Feedback pin voltage –0.3 25 V
Output voltage to ground, steady-state –1 V
Power dissipation Internally limited
Lead temperature KTW package Vapor phase (60 s) 215 °C
Infrared (10 s) 245
NDZ package, soldering (10 s) 260
Maximum junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) Voltage internally clamped. If clamp voltage is exceeded, limit current to a maximum of 1 mA.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Operating Conditions

MIN MAX UNIT
Supply voltage 4.5 40 V
Temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) LM2596 UNIT
KTW (TO-263) NDZ (TO-220)
7 PINS 7 PINS
RθJA Junction-to-ambient thermal resistance(2)(3) See(4) 50 °C/W
See(5) 50
See(6) 30
See(7) 20
RθJC(top) Junction-to-case (top) thermal resistance 2 2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal impedance is calculated in accordance to JESD 51-7.
(3) Thermal Resistances were simulated on a 4-layer, JEDEC board.
(4) Junction to ambient thermal resistance (no external heat sink) for the package mounted TO-220 package mounted vertically, with the leads soldered to a printed circuit board with (1 oz.) copper area of approximately 1 in2.
(5) Junction to ambient thermal resistance with the TO-263 package tab soldered to a single sided printed circuit board with 0.5 in2 of 1-oz copper area.
(6) Junction to ambient thermal resistance with the TO-263 package tab soldered to a single sided printed circuit board with 2.5 in2 of 1-oz copper area.
(7) Junction to ambient thermal resistance with the TO-263 package tab soldered to a double sided printed circuit board with 3 in2 of 1-oz copper area on the LM2596S side of the board, and approximately 16 in2 of copper on the other side of the PCB.

7.5 Electrical Characteristics – 3.3-V Version

Specifications are for TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS(3) (see Figure 35 for test circuit)
VOUT Output voltage 4.75 V ≤ VIN ≤ 40 V,
0.2 A ≤ ILOAD ≤ 3 A
TJ = 25°C 3.168 3.3 3.432 V
–40°C ≤ TJ ≤ 125°C 3.135 3.465
η Efficiency VIN = 12 V, ILOAD = 3 A 73%
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in Figure 35, system performance is shown in the test conditions column.

7.6 Electrical Characteristics – 5-V Version

Specifications are for TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS(3) (see Figure 35 for test circuit)
VOUT Output voltage 7 V ≤ VIN ≤ 40 V,
0.2 A ≤ ILOAD ≤ 3 A
TJ = 25°C 4.8 5 5.2 V
–40°C ≤ TJ ≤ 125°C 4.75 5.25
η Efficiency VIN = 12 V, ILOAD = 3 A 80%
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in Figure 35, system performance is shown in the test conditions column.

7.7 Electrical Characteristics – 12-V Version

Specifications are for TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS(3) (see Figure 35 for test circuit)
VOUT Output voltage 15 V ≤ VIN ≤ 40 V,
0.2 A ≤ ILOAD ≤ 3 A
TJ = 25°C 11.52 12 12.48 V
–40°C ≤ TJ ≤ 125°C 11.4 12.6
η Efficiency VIN = 25 V, ILOAD = 3 A 90%
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in Figure 35, system performance is shown in the test conditions column.

7.8 Electrical Characteristics – Adjustable Voltage Version

Specifications are for TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS(3) (see Figure 35 for test circuit)
VFB Feedback voltage 4.5 V ≤ VIN ≤ 40 V, 0.2 A ≤ ILOAD ≤ 3 A 1.23 V
VOUT programmed for 3 V
(see Figure 35 for test circuit)
TJ = 25°C 1.193 1.267
–40°C ≤ TJ ≤ 125°C 1.18 1.28
η Efficiency VIN = 12 V, VOUT = 3 V, ILOAD = 3 A 73%
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in Figure 35, system performance is shown in the test conditions column.

7.9 Electrical Characteristics – All Output Voltage Versions

Specifications are for TJ = 25°C, ILOAD = 500 mA, VIN = 12 V for the 3.3-V, 5-V, and adjustable version, and VIN = 24 V for the 12-V version (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
DEVICE PARAMETERS
Ib Feedback bias current Adjustable version only,
VFB = 1.3 V
TJ = 25°C 10 50 nA
–40°C ≤ TJ ≤ 125°C 100
fO Oscillator frequency(3) TJ = 25°C 127 150 173 kHz
–40°C ≤ TJ ≤ 125°C 110 173
VSAT Saturation voltage(4) (5) IOUT = 3 A TJ = 25°C 1.16 1.4 V
–40°C ≤ TJ ≤ 125°C 1.5
DC Max duty cycle (ON)(5) 100%
Min duty cycle (OFF)(6) 0%
ICL Current limit(4) (5) Peak current TJ = 25°C 3.6 4.5 6.9 A
–40°C ≤ TJ ≤ 125°C 3.4 7.5
IL Output leakage current(4) (6) Output = 0 V, VIN = 40 V 50 μA
Output = –1 V 2 30 mA
IQ Operating quiescent current(6) See (6) 5 10 mA
ISTBY Current standby quiescent ON/OFF pin = 5 V (OFF)(7) TJ = 25°C 80 200 μA
–40°C ≤ TJ ≤ 125°C 250 μA
SHUTDOWN/SOFT-START CONTROL (see Figure 35 for test circuit)
VIH ON/OFF pin logic input threshold voltage Low (regulator ON) TJ = 25°C 1.3 V
–40°C ≤ TJ ≤ 125°C 0.6
VIL High (regulator OFF) TJ = 25°C 1.3 V
–40°C ≤ TJ ≤ 125°C 2
IH ON/OFF pin input current VLOGIC = 2.5 V (regulator OFF) 5 15 μA
IL VLOGIC = 0.5 V (regulator ON) 0.02 5 μA
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) The switching frequency is reduced when the second stage current limit is activated. The amount of reduction is determined by the severity of current overload.
(4) No diode, inductor, or capacitor connected to output pin.
(5) Feedback pin removed from output and connected to 0 V to force the output transistor switch ON.
(6) Feedback pin removed from output and connected to 12 V for the 3.3-V, 5-V, and the adjustable versions, and 15 V for the 12-V version, to force the output transistor switch OFF.
(7) VIN = 40 V.

7.10 Typical Characteristics

See Figure 35 for test circuit
LM2596 01258304.png Figure 1. Normalized Output Voltage
LM2596 01258306.png Figure 3. Efficiency
LM2596 01258308.png Figure 5. Switch Current Limit
LM2596 01258310.png Figure 7. Operating Quiescent Current
LM2596 01258312.png Figure 9. Minimum Operating Supply Voltage
LM2596 01258314.png Figure 11. ON/OFF Pin Current (Sinking)
LM2596 01258316.png Figure 13. Feedback Pin Bias Current
LM2596 01258305.png Figure 2. Line Regulation
LM2596 01258307.png Figure 4. Switch Saturation Voltage
LM2596 01258309.png Figure 6. Dropout Voltage
LM2596 01258311.png Figure 8. Shutdown Quiescent Current
LM2596 01258313.png Figure 10. ON/OFF Threshold Voltage
LM2596 01258315.png Figure 12. Switching Frequency