The LM3481 device uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In a typical application circuit, the peak current through the external MOSFET is sensed through an external sense resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM comparator.
At the start of any switching cycle, the oscillator sets the RS latch using the SET/Blank-out and switch logic blocks. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is reset and the external MOSFET turns off.
The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 18. These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a short duration after the latch is set. This duration, called the blank-out time, is typically 250 ns and is specified as tmin (on) in the Electrical Characteristics section.
Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external MOSFET is on during the blank-out time is more than what is delivered to the load. An overvoltage comparator inside the LM3481 prevents the output voltage from rising under these conditions by sensing the feedback (FB pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to the nominal value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency.
The LM3481 has overvoltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (FB). If at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See the Electrical Characteristics section for limits on VFB and VOVP.
OVP will cause the drive pin (DR) to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage will drop. The LM3481 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)). See the Electrical Characteristics section for limits on VOVP(HYS). The Error Amplifier is operationnal during OVP events.
The internal bias of the LM3481 comes from either the internal bias voltage generator as shown in the block diagram or directly from the voltage at the VIN pin. At input voltages lower than 6 V the internal IC bias is the input voltage and at voltages above 6 V the internal bias voltage generator of the LM3481 provides the bias. The voltage for the gate driver is output on the VCC pin for compensation by an external capacitor (0.47µF to 4.7µF depending on the FET requirements). Biasing the VCC pin by an external voltage source should not be attempted.
The LM3481 uses a current mode control scheme. The main advantages of current mode control are inherent cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is easy to parallel power stages using current mode control because current sharing is automatic. However there is a natural instability that will occur for duty cycles, D, greater than 50% if additional slope compensation is not addressed as described below.
The current mode control scheme samples the inductor current, IL, and compares the sampled signal, Vsamp, to a internally generated control signal, Vc. The current sense resistor, RSEN, as shown in Figure 23, converts the sampled inductor current, IL, to the voltage signal, Vsamp, that is proportional to IL such that:
The rising and falling slopes, M1 and −M2 respectively, of Vsamp are also proportional to the inductor current rising and falling slopes, Mon and −Moff respectively. Where Mon is the inductor slope during the switch on-time and −Moff is the inductor slope during the switch off-time and are related to M1 and −M2 by:
For the boost topology:
Current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 20, where the control signal slope, MC, equals zero. In Figure 20, a small increase in the load current causes the sampled signal to increase by ΔVsamp0. The effect of this load change, ΔVsamp1, at the end of the first switching cycle is :
From Equation 9, when D > 0.5, ΔVsamp1 will be greater than ΔVsamp0. In other words, the disturbance is divergent. So a very small perturbation in the load will cause the disturbance to increase. To ensure that the perturbed signal converges we must maintain:
To prevent the subharmonic oscillations, a compensation ramp is added to the control signal, as shown in Figure 21.
With the compensation ramp, ΔVsamp1 and the convergence criteria are expressed by,
The compensation ramp has been added internally in the LM3481. The slope of this compensation ramp has been selected to satisfy most applications, and it's value depends on the switching frequency. This slope can be calculated using the formula:
To provide the user additional flexibility, a patented scheme has been implemented inside the IC to increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RSL(as shown in Figure 23) increases the amplitude of the compensation ramp as shown in Figure 22.
K = 40 µA typically and changes slightly as the switching frequency changes. Figure 24 shows the effect the current K has on ΔVSLand different values of RSL as the switching frequency changes.
A more general equation for the slope compensation ramp, MC, is shown below to include ΔVSL caused by the resistor RSL.
It is good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation. Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the error voltage to a saw tooth waveform rather than the inductor current.
The switching frequency of the LM3481 can be adjusted between 100 kHz and 1 MHz using a single external resistor. This resistor must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 25. Refer to the Typical Characteristics to determine the value of the resistor required for a desired switching frequency.
Equation 16 can also be used to estimate the frequency adjust resistor.
Where fS is in kHz and RFA in kΩ.
The LM3481 can be synchronized to an external clock. The external clock must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 26. The frequency adjust resistor may remain connected while synchronizing a signal, therefore if there is a loss of signal, the switching frequency will be set by the frequency adjust resistor.
It is also necessary to have the width of the synchronization pulse wider than the duty cycle of the converter and to have the synchronization pulse width ≥ 300 ns.
The FA/SYNC/SD pin also functions as a shutdown pin. If a high signal (refer to the Electrical Characteristics section for definition of high signal) appears on the FA/SYNC/SD pin, the LM3481 stops switching and goes into a low current mode. The total supply current of the IC reduces to 5 µA, typically, under these conditions.
Figure 27 and Figure 28 show an implementation of a shutdown function when operating in frequency adjust mode and synchronization mode, respectively. In frequency adjust mode, connecting the FA/SYNC/SD pin to ground forces the clock to run at a certain frequency. Pulling this pin high shuts down the IC. In frequency adjust or synchronization mode, a high signal for more than 30 µs shuts down the IC.
The UVLO pin provides user programmable enable and shutdown thresholds. The UVLO pin is compared to an internal reference of 1.43 V (typical), and a resistor divider programs the enable threshold, VEN. When the IC is enabled, a 5-μA current is sourced out of the UVLO pin, which effectively causes a hysteresis, and the UVLO shutdown threshold, VSH, is now lower than the enable threshold. Setting these thresholds requires two resistors connected from the VIN pin to the UVLO pin and from the UVLO pin to GND (see Figure 29). Select the desired enable, VEN, and UVLO shutdown, VSH, threshold voltages and use the Equation 17 and Equation 18 to determine the resistance values:
If the system is designed to work over wide input voltages, the voltage at the UVLO pin could exceed the voltage limit for the UVLO pin. In this case a zener diode can be connected between the UVLO pin and ground to prevent the UVLO voltage from rising above the maximum value.
If the UVLO pin function is not desired, select R8 and R7 of equal magnitude greater than 100 kΩ. This will allow VIN to be in control of the UVLO thresholds. The UVLO pin may also be used to implement the enable/disable function. If a signal pulls the UVLO pin below the 1.43 V (typical) threshold, the converter will be disabled.
When the voltage across the sense resistor (measured on the ISEN Pin) exceeds 220 mV, short-circuit current limit gets activated. A comparator inside the LM3481 reduces the switching frequency by a factor of 8 and maintains this condition until the short is removed.
The device is set to run as soon as the input voltage crosses above the UVLO set point and at a frequency set according to the FA/SYNC/SD pin pull-down resistor or to run at a frequency set by the waveform applied to the FA/SYNC/SD pin.
If the FA/SYNC/SD pin is pulled high, the LM3481 enters shut-down mode.