SNVSB97A December 2018 – September 2021 LM34936-Q1
PRODUCTION DATA
This section presents the control loop compensation design procedure for the LM34936-Q1 buck-boost controller. The LM34936-Q1 operates mainly in Buck or Boost modes, separated by a transition region, and therefore, the control loop design is done for both Buck and Boost operating modes. Then, a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in Boost mode.
The boost power stage output pole location is given by:
where
The boost power stage ESR zero location is given by:
The boost power stage RHP zero location is given by:
where
The buck power stage output pole location is given by:
The buck power stage ESR zero location is the same as the boost power stage ESR zero.
It is clear from Equation 37 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design, the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:
For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum duty cycle (D_{MAX}) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (f_{RHP}/3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.
The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:
If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the crossover, the compensation gain resistor R_{c1} is calculated using the approximation:
where
The compensation capacitor C_{c1} is then calculated from:
The standard values of compensation components are selected to be R_{c1} = 10 kΩ and C_{c1} = 33 nF.
A high frequency pole (f_{pc2}) is placed using a capacitor (C_{c2}) in parallel with R_{c1} and C_{c1}. Set the frequency of this pole at seven to 10 times of f_{bw} to provide attenuation of switching ripple and noise on COMP while avoiding excessive phase loss at the crossover frequency. For a target f_{pc2} = 28 kHz, C_{c2} is calculated using this equation:
Select a standard value of 560 pF for C_{c2}. These values provide a good starting point for the compensation design. Each design should be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.