SNVSB97A December   2018  – September 2021 LM34936-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 7.3.2  VCC Regulator and Optional BIAS Input
      3. 7.3.3  Enable/UVLO
      4. 7.3.4  Soft Start
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Average Input/Output Current Limiting
      7. 7.3.7  Operation Above 28-V Input
      8. 7.3.8  CCM Operation
      9. 7.3.9  Frequency and Synchronization (RT/SYNC)
      10. 7.3.10 Frequency Dithering
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Power Good (PGOOD)
      13. 7.3.13 Gm Error Amplifier
      14. 7.3.14 Integrated Gate Drivers
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown, Standby, and Operating Modes
      2. 7.4.2 MODE Pin Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design with WEBENCH Tools
        2.  Frequency
        3.  VOUT
        4.  Inductor Selection
        5.  Output Capacitor
        6.  Input Capacitor
        7.  Sense Resistor (RSENSE)
        8.  Slope Compensation
        9.  UVLO
        10. Soft-Start Capacitor
        11. Dither Capacitor
        12. MOSFETs QH1 and QL1
        13. MOSFETs QH2 and QL2
        14. Frequency Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Frequency Compensation

This section presents the control loop compensation design procedure for the LM34936-Q1 buck-boost controller. The LM34936-Q1 operates mainly in Buck or Boost modes, separated by a transition region, and therefore, the control loop design is done for both Buck and Boost operating modes. Then, a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in Boost mode.

The boost power stage output pole location is given by:

Equation 35. GUID-86E32853-0152-4AFC-B801-E30419D56A25-low.gif


  • ROUT = 2 Ω corresponds to the maximum load of 6 A.

The boost power stage ESR zero location is given by:

Equation 36. GUID-90BBBABD-FE08-426C-84AB-747F72735938-low.gif

The boost power stage RHP zero location is given by:

Equation 37. GUID-5DA42572-B6B5-4C04-89F9-31A825123F0F-low.gif


  • DMAX is the maximum duty cycle at the minimum VIN.

The buck power stage output pole location is given by:

Equation 38. GUID-9C3267A7-4D4E-44BC-99AE-3EEFDE0828E6-low.gif

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 37 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design, the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:

Equation 39. GUID-EE24DA47-0F09-44D7-A515-B5620C6D9CA2-low.gif

For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (fRHP/3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:

Equation 40. GUID-E8A1C084-A40A-48FB-935E-767AC9F762AE-low.gif

If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the crossover, the compensation gain resistor Rc1 is calculated using the approximation:

Equation 41. GUID-9088D48F-3291-4C8B-A65A-2DE902CA9756-low.gif


  • DMAX is the maximum duty cycle at the minimum VIN in Boost mode.
  • ACS is the current sense amplifier gain.

The compensation capacitor Cc1 is then calculated from:

Equation 42. GUID-D384860F-CC52-4E67-847D-638D52F00557-low.gif

The standard values of compensation components are selected to be Rc1 = 10 kΩ and Cc1 = 33 nF.

A high frequency pole (fpc2) is placed using a capacitor (Cc2) in parallel with Rc1 and Cc1. Set the frequency of this pole at seven to 10 times of fbw to provide attenuation of switching ripple and noise on COMP while avoiding excessive phase loss at the crossover frequency. For a target fpc2 = 28 kHz, Cc2 is calculated using this equation:

Equation 43. GUID-BBC493F9-2D17-41D9-8CAE-5580617B8D3A-low.gif

Select a standard value of 560 pF for Cc2. These values provide a good starting point for the compensation design. Each design should be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.