SNVSBU7 September   2020 LM34966-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 8.3.3  Soft Start (SS Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (UVLO/SYNC/EN Pin)
      6. 8.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 8.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 8.3.9  Power-Good Indicator (PGOOD Pin)
      10. 8.3.10 Hiccup Mode Overload Protection
      11. 8.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (GATE Pin)
      13. 8.3.13 Overvoltage Protection (OVP)
      14. 8.3.14 Thermal Shutdown (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Power-On Hours (POH)
    2. 9.2 Application Information
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Custom Design With WEBENCH® Tools
        2. 9.3.2.2 Recommended Components
        3. 9.3.2.3 Inductor Selection (LM)
        4. 9.3.2.4 Output Capacitor (COUT)
        5. 9.3.2.5 Input Capacitor
        6. 9.3.2.6 MOSFET Selection
        7. 9.3.2.7 Diode Selection
        8. 9.3.2.8 Efficiency Estimation
      3. 9.3.3 Application Curve
    4. 9.4 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7 Current Limit and Minimum On-time (CS Pin)

The device provides cycle-by-cycle peak current limit protection that turns off the MOSFET when the sum of the inductor current and the programmable slope compensation ramp reaches the current limit threshold (VCLTH). Peak inductor current limit (IPEAK-CL) in steady state is calculated as shown in Equation 10.

Equation 10. GUID-5DD45E99-6F1A-4079-BFE1-C91D10B41491-low.gif

The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense resistor. The estimated duty cycle is calculated as shown in Equation 11.

Equation 11. GUID-19EF12F0-9623-43D0-88E6-96E003595BFA-low.gif

Boost converters have a natural pass-through path from the supply to the load through the high-side power diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot provide current limit protection when the output voltage is close to or less than the input supply voltage. The minimum on-time is shown in Figure 7-12 and is calculated as Equation 12.

Equation 12. GUID-CE5F41FB-0597-4C56-8D9E-C03F5E754B75-low.gif

If required, a small external RC filter (RF, CF) at the CS pin can be added to overcome the large leading edge spike of the current sense signal. Select an RF value which is in the range of 10 Ω to 200 Ω and a CF value in the rage of 100 pF to 2 nF. Because of the effect of this RC filter, the peak current limit is not valid when the on-time is less than 2 × RF × CF. To fully discharge the CF during the off-time, the RC time constant should satisfy the following inequality.

Equation 13. GUID-FCCD7CDD-0FF6-4FCD-8083-3C418486C66F-low.gif