SNVSB87 November   2018 LM3880-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simple Power Supply Sequencing
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Timing Requirements
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Pin Operation
      2. 7.3.2 Incomplete Sequence Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up With EN Pin
      2. 7.4.2 Power Down With EN Pin
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Open Drain Flags Pullup
      2. 8.1.2 Enable the Device
    2. 8.2 Typical Application
      1. 8.2.1 Simple Sequencing of Three Power Supplies
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Sequencing Using Independent Flag Supply
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enable Pin Operation

The timing sequence of the LM3880-Q1 is controlled by the assertion of the enable signal. The enable pin is designed with an internal comparator, referenced to a bandgap voltage (1.25 V), to provide a precision threshold. This allows a delayed timing to be externally set using a capacitor or to start the sequencing based on a certain event, such as a line voltage reaching 90% of nominal. For an additional delayed sequence from the rail powering VCC, simply attach a capacitor to the EN pin as shown in Figure 11.

LM3880-Q1 capacitor_timing_snvs451.gifFigure 11. Capacitor Timing

Using the internal pullup current source to charge the external capacitor (CEN) the enable pin delay can be calculated by Equation 1:

Equation 1. LM3880-Q1 20192616.gif

A resistor divider can also be used to enable the device based on a certain voltage threshold. Take care when sizing the resistor divider to include the effects of the internal current source.

One of the features of the EN pin is that it provides glitch free operation. The first timer will start counting at a rising threshold, but will always reset if the EN pin is deasserted before the first output flag is released. This can be shown in Figure 12:

LM3880-Q1 20192617.gifFigure 12. EN Glitch