SLOS456N January   2005  – October 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  LM4040A20I, LM4040B20I Electrical Characteristics
    6. 6.6  LM4040C20I, LM4040D20I Electrical Characteristics
    7. 6.7  LM4040C20Q, LM4040D20Q Electrical Characteristics
    8. 6.8  LM4040A25I, LM4040B25I Electrical Characteristics
    9. 6.9  LM4040C25I, LM4040D25I Electrical Characteristics
    10. 6.10 LM4040C25Q, LM4040D25Q Electrical Characteristics
    11. 6.11 LM4040A30I, LM4040B30I Electrical Characteristics
    12. 6.12 LM4040C30I, LM4040D30I Electrical Characteristics
    13. 6.13 LM4040C30Q, LM4040D30Q Electrical Characteristics
    14. 6.14 LM4040A41I, LM4040B41I Electrical Characteristics
    15. 6.15 LM4040C41I, LM4040D41I Electrical Characteristics
    16. 6.16 LM4040A50I, LM4040B50I Electrical Characteristics
    17. 6.17 LM4040C50I, LM4040D50I Electrical Characteristics
    18. 6.18 LM4040C50Q, LM4040D50Q Electrical Characteristics
    19. 6.19 LM4040A82I, LM4040B82I Electrical Characteristics
    20. 6.20 LM4040C82I, LM4040D82I Electrical Characteristics
    21. 6.21 LM4040A10I, LM4040B10I Electrical Characteristics
    22. 6.22 LM4040C10I, LM4040D10I Electrical Characteristics
    23. 6.23 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shunt Reference
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 LM4040 Voltage and Accuracy Choice
        2. 8.2.2.2 Cathode and Load Currents
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 SOT-23 Connections
        5. 8.2.2.5 Start-Up Characteristics
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

Figure 10 shows an example of a PCB layout of LM4040XXXDBZ. Some key Vref noise considerations are:

  • Connect a low-ESR, 0.1-μF (CL) ceramic bypass capacitor on the cathode pin node.
  • Decouple other active devices in the system per the device specifications.
  • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible and only make perpendicular crossings when absolutely necessary.

Layout Example

LM4040A LM4040B LM4040C LM4040D layout_lm.gif Figure 10. DBZ Layout example