SNVSA99C July   2015  – November 2017 LM43600-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (ENABLE)
      5. 7.3.5  VCC, UVLO and BIAS
      6. 7.3.6  Soft-Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Switching Frequency (RT) and Synchronization (SYNC)
      8. 7.3.8  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage (BOOT)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Stand-by Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 Light Load Operation
      6. 7.4.6 Self-Bias Mode
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Output Voltage Setpoint
        3.  Switching Frequency
        4.  Input Capacitors
        5.  Inductor Selection
        6.  Output Capacitor Selection
        7.  Feedvorward Capacitor
        8.  Bootstrap Capacitors
        9.  VCC Capacitor
        10. BIAS Capacitors
        11. Soft-Start Capacitors
        12. Undervoltage Lockout Setpoint
        13. PGOOD
      3. 8.2.3 Application Performance Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Development Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The LM43600-Q1 regulator is an easy to use synchronous step-down DC-DC converter that operates from 3.5-V to 36-V supply voltage. It is capable of delivering up to 0.5-A DC load current with exceptional efficiency and thermal performance in a very small solution size. An extended family is available in 1-A, 2-A, and 3-A load options in pin-to-pin compatible packages.

The LM43600-Q1 employs fixed frequency peak current mode control with discontinuous conduction mode (DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load range. The device is internally compensated, which reduces design time, and requires fewer external components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, RT. It defaults at 500 kHz without RT. The LM43600-Q1 is also capable of synchronization to an external clock within the 200 kHz to 2.2 MHz frequency range. The wide switching frequency range allows the device to be optimized to fit small board space at higher frequency, or high efficient power conversion at lower frequency.

Optional features are included for more comprehensive system requirements, including power-good (PGOOD) flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking. These features provide a flexible and easy to use platform for a wide range of applications. Protection features include over temperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and short-circuit protection with hiccup mode.

The family requires few external components and the pin arrangement was designed for simple, optimum PCB layout. The LM43600-Q1 device is available in the 16-pin, leaded HTSSOP (PWP) package (6.6 mm × 5.5 mm × 1.2 mm) with 0.65-mm lead pitch.

Functional Block Diagram

LM43600-Q1 bd_snvsa13.gif

Feature Description

Fixed Frequency Peak Current Mode Controlled Step-Down Regulator

The following operating description of the LM43600-Q1 refers to the Functional Block Diagram and to the waveforms in Figure 33. The LM43600-Q1 is a step-down buck regulator with both high-side (HS) switch and low-side (LS) switch (synchronous rectifier) integrated. The LM43600-Q1 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin voltage VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope (VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of Buck converters are defined as Duty Cycle D = tON / TSW, where tON is the HS switch ON-time and TSW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.

LM43600-Q1 SW_inductor_wvfrm_CCM_snvsa13.gif Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LM43600-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). At very light load, the LM43600-Q1 operates in PFM to maintain high efficiency, and the switching frequency decreases with reduced load current.

Light Load Operation

DCM operation is employed in the LM43600-Q1 when the inductor current valley reaches zero. The LM43600-Q1 is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch ON-time reduces with lower load current. When either the minimum HS switch ON-time (TON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency will decrease to maintain regulation. At this point, the LM43600-Q1 operates in PFM. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching frequency decreases with decreased load current.

LM43600-Q1 43600_5V_1MHz_FreqPFM.png Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation
VOUT = 5 V FS = 1 MHz

In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed at VOUT. See Typical Characteristics for typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load at output is recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM43600-Q1 may not enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM43600-Q1 is operating in PFM mode at higher VIN, it will remain in PFM operation when VIN is reduced.

Adjustable Output Voltage

The voltage regulation loop in the LM43600-Q1 regulates output voltage by maintaining the voltage on FB pin (VFB) to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio from output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM43600-Q1 to ground with the mid-point connecting to the FB pin.

LM43600-Q1 output_volt_set_snvsa13.gif Figure 35. Output Voltage Setting

The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage is 1.016 V typically. To program the output voltage of the LM43600-Q1 to be a certain value VOUT, RFBB can be calculated with a selected RFBT by

Equation 1. LM43600-Q1 eq01_snvsa13.gif

The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature coefficient of 100 ppm or lower.

If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is broken. If the FB pin is shorted to ground, the output voltage will be driven close to VIN, since the regulator sees very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged under such a condition. Do not short FB pin to ground when the LM43600-Q1 is enabled. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout section.

Enable (ENABLE)

Voltage on the ENABLE pin (VEN) controls the ON or OFF functionality of the LM43600-Q1. Applying a voltage less than 0.4 V to the ENABLE input shuts down the operation of the LM43600-Q1. In shutdown mode the quiescent current drops to typically 1.1 µA at VIN = 12 V.

The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The switching action and output regulation are enabled when VEN is greater than 2.1 V (typical). The LM43600-Q1 supplies regulated output voltage when enabled and output current up to 0.5 A.

The ENABLE pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the LM43600-Q1 is to connect the ENABLE pin to VIN pins directly. This allows self-start-up when VIN is within the operation range.

Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 36 to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing and protection.

LM43600-Q1 vin_uvlo_snvsa13.gif Figure 36. System UVLO By Enable Dividers


The LM43600-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. A high quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM43600-Q1.

Undervoltage lockout (UVLO) prevents the LM43600-Q1 from operating until the VCC voltage exceeds 3.14 V (typical). The VCC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shuting down due to temperary VIN droops.

The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO - VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve LM43600-Q1 efficiency, especially at light load. It is recommended to tie the BIAS pin to VOUT when VOUT ≥ 3.3V. The BIAS pin should be grounded in applications with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, a 1µF to 10µF high quality ceramic capacitor is recommended to bypass the BIAS pin to ground.

Soft-Start and Voltage Tracking (SS/TRK)

The LM43600-Q1 has a flexible and easy to use start up rate control pin: SS/TRK. Soft-start feature is to prevent inrush current impacting the LM43600-Q1 and its supply when power is first applied. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up.

The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM43600-Q1 will employ the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically.

In applications with a large amount of output capacitors, or higher VOUT, or other special requirements, the soft-start time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-start time further reduces the supply current needed to charge up output capacitors and supply any output loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control the ramp-up rate of the output voltage. For a desired soft start time tSS, the capacitance for CSS can be found by

Equation 2. LM43600-Q1 eq02_snvsa13.gif

The soft start capacitor CSS is discharged by an internal FET when VOUT is shutdown by hiccup protection due to excessive load, temperature shutdown due to overheating or ENABLE = logic low. A large CSS cap will take a long time to discharge when ENABLE is toggled low. If ENABLE is toggled high again before the CSS is completely discharged, then the next resulting soft-start ramp will follow the internal soft-start ramp. Only when the soft-start voltage reaches the left-over voltage on CSS, will the output follow the ramp programmed by CSS. This behavior will look as if there are two slopes at startup. If this is not acceptable by a certain application, a R-C low-pass filter can be added to ENABLE to slow down the shutting down of VCC, which allows more time to discharge CSS.

The LM43600-Q1 is capable of start up into prebiased output conditions. When the inductor current reaches zero, the LS switch will be turned off to avoid negative current conduction. This operation mode is also called diode emulation mode. It is built-in by the DCM operation in light loads. With a prebiased output voltage, the LM43600-Q1 will wait until the soft-start ramp allows regulation above the prebiased voltage and then follow the soft-start ramp to the regulation level.

When an external voltage ramp is applied to the SS/TRK pin, the LM43600-Q1 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage seen by the SS/TRK pin should not fall below 1.2 V to avoid abnormal operation.

LM43600-Q1 soft_start_track_snvsa13.gif Figure 37. Soft Start Tracking External Ramp

VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 38 shows the case when VOUT ramps slower than the internal ramp, while Figure 39 shows when VOUT ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection during start-up. Use with special care.

LM43600-Q1 tracking_slow_snvsa13.gif Figure 38. Tracking with Longer Start-up Time Than The Internal Ramp
LM43600-Q1 tracking_fast_snvsa13.gif Figure 39. Tracking with Shorter Start-up Time Than The Internal Ramp

Switching Frequency (RT) and Synchronization (SYNC)

The switching frequency of the LM43600-Q1 can be programmed by the impedance RT from the RT pin to ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the LM43600-Q1 will operate at 500 kHz default switching frequency. The RT pin is not designed to be shorted to ground.

For a desired frequency, typical RT resistance can be found by Equation 3.

Equation 3. RT(kΩ) = 40200 / Freq (kHz) - 0.6

Figure 40 shows RT resistance vs switching frequency FS curve.

LM43600-Q1 Rt_Fs_Curve.png Figure 40. RT Resistance vs Switching Frequency

Table 1 provides typical RT values for a given FS.

Table 1. Typical Frequency Setting RT Resistance

FS (kHz) RT (kΩ)
200 200
350 115
500 80.6
750 53.6
1000 39.2
1500 26.1
2000 19.6
2200 17.8

The LM43600-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz. Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. The SYNC pin should be grounded if not used.

LM43600-Q1 freq_sync_snvsa13.gif Figure 41. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM43600-Q1 will switch at the frequency programmed by the RT resistor after a time-out period. It is recommended to connect a resistor RT to the RT pin such that the internal oscillator frequency is the same as the target clock frequency when the LM43600-Q1 is synchronized to an external clock. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. The choice of switching frequency may also be limited if an operating condition triggers TON-MIN or TOFF-MIN.

Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions

Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN is typically 125 ns in the LM43600-Q1. Minimum OFF-time, TOFF-MIN, is the smallest duration that the HS switch can be off. TOFF-MIN is typically 200 ns in the LM43600-Q1.

In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is

Equation 4. DMIN = TON-MIN × FS

And the maximum duty cycle allowed is

Equation 5. DMAX = 1 - TOFF-MIN × FS

Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LM43600-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when TOFF-MIN is reached. The switching frequency will decrease once longer duty cycle is needed under low VIN conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the synchronization clock. Such wide range of frequency foldback allows the LM43600-Q1 output voltage to stay in regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See Typical Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operating supply voltage can be found by

Equation 6. VIN-MAX = VOUT / (FS × TON-MIN )

At lower supply voltage, the switching frequency will decrease once TOFF-MIN is tripped. The minimum VIN without frequency foldback can be approximated by

Equation 7. VIN-MIN = VOUT / (1 – FS × TOFF-MIN )

Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Figure 42 gives an example of how FS decreases with decreasing supply voltage VIN at dropout operation.

LM43600-Q1 43600_5V_1MHz_Freq_Drop.png Figure 42. Switching Frequency Decreases in Dropout Operation
VOUT = 5 V FS = 1 MHz

Internal Compensation and CFF

The LM43600-Q1 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel with the top resistor divider RFBT for optimum transient performance as shown in Figure 43.

LM43600-Q1 feedfwd_capacitor_snvsa13.gif Figure 43. Feedforward Capacitor for Loop Compensation

The feedforward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by

Equation 8. fZ-CFF = 1 / (2π × RFBT × CFF).

An additional pole is also introduced with CFF at the frequency of

Equation 9. fP-CFF = 1 / (2π × CFF × (RFBT // RFBB)).

Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.

Designs with different combinations of output capacitors need different CFF. Different types of capacitors have different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency

Equation 10. fZ-ESR = 1 / ( 2π × ESR × COUT)

would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any CFF.

The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, CFF should be calculated based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See Detailed Design Procedure for the calculation of CFF.

Bootstrap Voltage (BOOT)

The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW + VCC). The boot diode is integrated on the LM43600-Q1 die to minimize the bill of material (BOM). A synchronous switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. TI recommends a high-quality ceramic 0.47-µF, 6.3-V or higher capacitor CBOOT.

Power Good (PGOOD)

The LM43600-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage. Voltage seen by the PGOOD pin should never exceed 12 V. A resistor divider pair can be used to divide the voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.

When the FB voltage is within the power-good band, +4% above and -4% below the internal reference VREF typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the voltage level defined by the pull up resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or –10 % below VREF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be pulled low to indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch delay.

Overcurrent and Short-Circuit Protection

The LM43600-Q1 is protected from over-current conditions by cycle-by-cycle current limiting on both peak and valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over heating.

High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. See Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the peak current is proportional to the duty cycle.

When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch will not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILS-LIMIT. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. If the current of the LS switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup current protection mode will be activated. In hiccup mode, the regulator will be shutdown and kept off for 5.5 ms typically before the LM43600-Q1 tries to start again. If over-current or short-circuit fault condition still exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current conditions, prevents over heating and potential damage to the device.

Hiccup is only activated when power-good flag is low. Under non-severe over-current conditions when VOUT has not fallen outside of the PGOOD tolerance band, the LM43600-Q1 will reduce the switching frequency and keep the inductor current valley clamped at the LS current limit level. This operation mode allows slight over current operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation will start after LS current limit is tripped 32 consecutive cycles.

Thermal Shutdown

Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown. The LM43600-Q1 will attempt to restart when the junction temperature drops to 150°C.

Device Functional Modes

Shutdown Mode

The EN pin provides electrical ON and OFF control for the LM43600-Q1. When VEN is below 0.4 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent current drops to 2.3 µA typically with VIN = 24 V. The LM43600-Q1 also employs undervoltage lockout protection. If VCC voltage is below the UVLO level, the output of the regulator will be turned off.

Stand-by Mode

The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).

Active Mode

The LM43600-Q1 is in Active Mode when VEN is above the precision enable threshold and VCC is above its UVLO level. The simplest way to enable the LM43600-Q1 is to connect the EN pin to VIN. This allows self start-up when the input voltage is in the operation range: 3.5 V to 60 V. See Enable (ENABLE) and VCC, UVLO and BIAS for details on setting these operating levels.

In Active Mode, depending on the load current, the LM43600-Q1 will be in one of four modes:

  1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple;
  2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation;
  3. Pulse Frequency Modulation (PFM) when switching frequency is decreased at very light load;
  4. Fold-back mode when switching frequency is decreased to maintain output regulation at lower supply voltage VIN.

CCM Mode

Continuous Conduction Mode (CCM) operation is employed in the LM43600-Q1 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the minimum HS switch ON-time (TON_MIN), the minimum HS switch OFF-time (TOFF_MIN) or LS current limit is exceeded. Output voltage ripple will be at a minimum in this mode and the maximum output current of 2 A can be supplied by the LM43600-Q1

Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM43600-Q1 will operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM operation, the LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and conduction losses are reduced in DCM, comparing to forced PWM operation at light load.

At even lighter current loads, Pulse Frequency Mode (PFM) is activated to maintain high efficiency operation. When the HS switch ON-time reduces to TON_MIN or peak inductor current reduces to its minimum IPEAK-MIN, the switching frequency will reduce to maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses.

Self-Bias Mode

For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to VOUT when VOUT ≥ 3.3 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal LDO are reduced and therefore the total efficiency is improved. These efficiency gains are more evident during light load operation. During this mode of operation, the LM43600-Q1 operates with a minimum quiescent current of 27 µA (typical). See VCC, UVLO and BIAS for more details.