SNVSA46B June 2014 – January 2018 LM46001
The LM46001 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. Place a high-quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3-V or higher rated voltage as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, left floating, connected to any other external supply, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM46001.
Undervoltage lockout (UVLO) prevents the LM46001 from operating until the VCC voltage exceeds 3.14 V (typical). The VCC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shutdown due to temporary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO × (VIN-LDO – VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve the LM46001 efficiency, especially at light load. TI recommends tying the BIAS pin to VOUT when VOUT ≥ 3.3 V. Ground the BIAS pin in applications with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, a 1-µF to 10-µF, high-quality ceramic capacitor is recommended to bypass the BIAS pin to ground.