SNVS480J January 2007 – July 2020 LM5022
The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4 V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0 V on the COMP pin results in a zero duty cycle at the controller output. For duty cycles greater than 50%, current mode control circuits can experience subharmonic oscillation. By adding an additional fixed-slope voltage ramp signal (slope compensation), this oscillation can be avoided. Proper slope compensation damps the double pole associated with current mode control (see the Control Loop Compensation section) and eases the design of the control loop compensator. The LM5022 generates the slope compensation with a sawtooth-waveform current source with a slope of 45 µA × ƒSW, generated by the clock (see Figure 12). This current flows through an internal 2-kΩ resistor to create a minimum compensation ramp with a slope of 100 mV × ƒSW (typical). The slope of the compensation ramp increases when external resistance is added for filtering the current sense (RS1) or in the position RS2. As shown in Figure 12 and the Functional Block Diagram, the sensed current slope and the compensation slope add together to create the signal used for current limiting and for the control loop itself.
In peak current mode control, the optimal slope compensation is proportional to the slope of the inductor current during the power switch off-time. For boost converters, the inductor current slope while the MOSFET is off is (VO – VIN) / L. This relationship is combined with the requirements to set the peak current limit and is used to select RSNS and RS2 in the Application and Implementation section.