SNVS655I June 2011 – January 2016 LM5066
PRODUCTION DATA.
The LM5066 is a hotswap with a PMBus interface that provides current, voltage, power, and status information to the host. As a hotswap, it is used to manage inrush current and protect in case of faults.
When designing a hotswap, three key scenarios should be considered:
All of these scenarios place a lot of stress on the hotswap MOSFET and take special care when designing the hotswap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the following sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends to use the LM5066 Design Calculator provided on the product page.
This section describes the design procedure for a 48-V, 10-A PMBUS hotswap design.
Table 46 summarizes the design parameters that must be known before designing a hotswap circuit. When charging the output capacitor through the hotswap MOSFET, the FET’s total energy dissipation equals the total energy stored in the output capacitor (1 / 2CV^{2}). Thus, both the input voltage and output capacitance determine the stress experienced by the MOSFET. The maximum load current drives the current limit and sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and thermal properties of the PCB (R_{θCA}) drive the selection of the MOSFET R_{DSON} and the number of MOSFETs used. R_{θCA} is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET. Note that the drain is not electrically connected to the ground plane, and thus the ground plane cannot be used to help with heat dissipation. This design example uses R_{θCA} = 30°C/W, which is similar to the LM5066 EVM. It is a good practice to measure the R_{θCA} of a given design after the physical PCBs are available.
Finally, it is important to understand what test conditions the hotswap needs to pass. In general, a hotswap is designed to pass both a hot-short and a start into a short, which are described in the previous section. Also, TI recommends to keep the load OFF until the hotswap is fully powered-up. Starting the load early causes unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start-up.
PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range | 40 to 60 V |
Maximum load current | 10 A |
Maximum output capacitance of the hotswap | 220 µF |
Maximum ambient temperature | 85°C |
MOSFET R_{θCA} (function of layout) | 30°C/W |
Pass hot-short on output? | Yes |
Pass a start into short? | Yes |
Is the load off until PG asserted? | Yes |
Can a hot board be plugged back in? | Yes |
LM5066 can be used with a VCL of 26 or 50 mV. Using the 26-mV threshold results in a lower R_{SNS} and lower I^{2}R losses, but using the 50-mV threshold would result in better current and power monitoring accuracy along with a lower minimum power limit . The 26-mV option is selected for this design by connecting the CL pin directly to V_{DD}. TI recommends to target a current limit that is at least 10% above the maximum load current to account for the tolerance of the LM5066 current limit. Targeting a current limit of 11 A, the sense resistor can be computed as follows:
Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 29.
The next larger available sense resistor should be chosen (3 mΩ in this case). The ratio of R_{1} and R_{2} can be computed as follows:
Note that the SENSE pin pulls 25 μA of current, which creates an offset across R_{2}. TI recommends to keep R_{2} below 10 Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance (R_{SNS,EFF}) using Equation 7 and use that in all equations instead of R_{SNS}.
Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the next smaller available sense resistor. For this application, a 2-mΩ resistor can be used for a 13-A current limit.
It is critical to select the correct MOSFET for a hotswap design. The device must meet the following requirements:
For this design, the PSMN4R8-100BSE was selected for its low R_{DSON} and superior SOA. After selecting the MOSFET, the maximum steady-state case temperature can be computed as follows:
Note that the R_{DSON} is a strong function of junction temperature, which for most D2PACK MOSFETs is very close to the case temperature. A few iterations of the previous equations may be necessary to converge on the final R_{DSON} and T_{C,MAX} value. According to the PSMN4R8-100BSE data sheet, it's R_{DSON} doubles at 110°C. Equation 9 uses this R_{DSON} value to compute the T_{C,MAX}. Note that the computed T_{C,MAX} is close to the junction temperature assumed for R_{DSON}. Thus, no further iterations are necessary.
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the LM5066 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (V_{SNS}) to a very-low value. V_{SNS} can be computed as shown in Equation 10.
To avoid significant degradation of the power limiting, TI does not recommend a V_{SNS} of less than 4 mV. Based on this requirement, the minimum allowed power limit can be computed as follows:
In most applications, the power limit can be set to P_{LIM,MIN} using Equation 12. Note that the P_{LIM} of the LM5066 will have some variations vs V_{DS} of the MOSFET due to a 1.5-mV systematic offset. Equation 12 sets R_{PWR} to make the actual power limit equal the programmed power limit at V_{IN} = V_{IN,MAX} and V_{OUT} = 0 V.
The closest available resistor should be selected. In this case, a 21-kΩ resistor was chosen.
The fault timer runs when the hotswap is in power limit or current limit, which is the case during start-up. Thus, the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (I_{LIM} × V_{DS} < P_{LIM}), the maximum start time can be computed with Equation 13.
For most designs (including this example), I_{LIM} × V_{DS} > P_{LIM}, so the hotswap starts in power limit and transitions into current limit. In that case, the maximum start time can be computed as in Equation 14.
Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up, TI recommends to set the fault time (t_{flt}) to be 2 × t_{start,max} or 6.76 ms. This accounts for the variation in power limit, timer current, and timer capacitance. Thus, C_{TIMER} can be computed as follows:
The next largest standards capacitor value for C_{TIMER} is chosen as 150 nF. After C_{TIMER} is chosen, the actual programmed fault time can be computed as follows:
When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all test conditions. During a hot-short the circuit breaker trips and the LM5066 restarts into power limit until the timer runs out. In the worst case, the MOSFET’s V_{DS} equals V_{IN,MAX}, I_{DS} equals P_{LIM} / V_{IN,MAX} and the stress event lasts for t_{flt}. For this design example, the MOSFET has 60 V, 2 A across it for 7.8 ms.
Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for 10 ms. For 7.8 ms, the SOA can be extrapolated by approximating SOA versus time as a power function as shown below:
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on T_{C,MAX} using Equation 18:
Based on this calculation, the MOSFET can handle 2.85 A, 60 V for 7.8 ms at elevated case temperature, but is only required to handle 2 A during a hot-short. Thus, there is good margin and the design is robust. In general, TI recommends that the MOSFET can handle 1.3× more than what is required during a hot-short. This provides margin to account for the variance of the power limit and fault time.
By programming the UVLO and OVLO thresholds, the LM5066 enables the series-pass device (Q_{1}) when the input supply voltage (V_{IN}) is within the desired operational range. If V_{IN} is below the UVLO threshold or above the OVLO threshold, Q_{1} is switched off, denying power to the load. Hysteresis is provided for each threshold.
The configuration shown in Figure 30 requires three resistors (R1 to R3) to set the thresholds.
The procedure to calculate the resistor values is as follows:
The lower OVLO threshold is calculated from:
When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following:
If all four thresholds must be accurately defined, the configuration in Figure 31 can be used.
The four resistor values are calculated as follows:
The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 32. Q1 is switched on when the VIN voltage reaches the POR_{EN} threshold (≊8.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.
The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in Option B or Option C.
For this design example, option B was used and the following options were targeted: V_{UVH} = 38 V, V_{UVL} = 35 V, V_{OVH} = 65 V, and V_{OVL} = 63 V. The V_{UVH} and V_{OVL} were chosen to be 5% below or above the input voltage range of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using the following equations:
Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74 kΩ.
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to V_{PGD} through the pullup resistor, R_{PG}, as shown in Figure 34. The pullup voltage (V_{PGD}) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a convenient choice for V_{PGD} as it allows interface to low voltage logic and avoids glitching on PGD during power-up. If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35(A), capacitor C_{PG} adds delay to the rising edge, but not to the falling edge. In Figure 35(B), the rising edge is delayed by R_{PG1} + R_{PG2} and C_{PG}, while the falling edge is delayed a lesser amount by R_{PG2} and C_{PG}. Adding a diode across R_{PG2} (Figure 35(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are computed using the following equations:
Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.
Proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in . The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shutts off. The TVS should be chosen to have minimal leakage current at V_{IN,MAX} and to clamp the voltage to under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice.
If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required across the LM5066’s output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off.
Figure 28 shows the schematic used to implement the requirements described in the previous section. In addition, Table 47 provides the final component values that were used to meet the design requirements for a 48-V, 10-A hotswap design. The application curves in the next section are based on these component values.
COMPONENT | VALUE | |
---|---|---|
R_{SNS} | 2 mΩ | |
R1 | 150 kΩ | |
R2 | 11.5 kΩ | |
R3 | 95.3 kΩ | |
R4 | 3.74 kΩ | |
R5 | 150 kΩ | |
R6 | 10.5 kΩ | |
R_{PWR} | 21 kΩ | |
Q1 | PSMN4R8-100BSEJ | |
Q2 | MMBT3904 | |
D1 | B380-13-F | |
Z1 | 5.0SMDJ60A | |
C_{TIMER} | 150 nF | |
Optional dv/dt circuit | DNP |
V_{IN} = 40V |
V_{IN} = 48V |
V_{IN} = 60V |