The LM5143-Q1 high-side and low-side gate drivers incorporate short
propagation delays, adaptive dead-time control, and low-impedance output stages
capable of delivering large peak currents with very fast rise and fall times to
facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high
di/dt can cause unacceptable ringing if the trace lengths and impedances are not
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:
- Loop 2: high-side MOSFET, Q1. During
the high-side MOSFET turnon, high current flows from the bootstrap (boot)
capacitor through the gate driver and high-side MOSFET, and back to the
negative terminal of the boot capacitor through the SW connection.
Conversely, to turn off the high-side MOSFET, high current flows from the
gate of the high-side MOSFET through the gate driver and SW, and back to the
source of the high-side MOSFET through the SW trace. Refer to loop 2 of
- Loop 3: low-side MOSFET, Q2. During
the low-side MOSFET turnon, high current flows from the VCC decoupling
capacitor through the gate driver and low-side MOSFET, and back to the
negative terminal of the capacitor through ground. Conversely, to turn off
the low-side MOSFET, high current flows from the gate of the low-side MOSFET
through the gate driver and GND, and back to the source of the low-side
MOSFET through ground. Refer to loop 3 of Figure 11-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.
- Connections from gate driver outputs, HO1/2,
HOL1/2, LO1/2, and LOL1/2 to the respective gates of the high-side or
low-side MOSFETs must be as short as possible to reduce series parasitic
inductance. Be aware that peak gate drive currents can be as high as 4.25 A.
Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at
least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate
traces as a differential pair from the LM5143-Q1 to the high-side MOSFET,
taking advantage of flux cancellation.
- Minimize the current loop path from the VCC and
HB pins through their respective capacitors as these provide the high
instantaneous current, up to 4.25 A, to charge the MOSFET gate capacitances.
Specifically, locate the bootstrap capacitor, CBST, close to the
HB and SW pins of the LM5143-Q1 to minimize the area of
loop 2 associated with the high-side driver. Similarly, locate the VCC
capacitor, CVCC, close to the VCC and PGND pins of the LM5143-Q1 to minimize the area of
loop 3 associated with the low-side driver.