SNVSB29C October   2018  – June 2021 LM5143-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Enable (EN1, EN2)
      4. 8.3.4  Power Good Monitor (PG1, PG2)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Clock Synchronization (DEMB)
      7. 8.3.7  Synchronization Out (SYNCOUT)
      8. 8.3.8  Spread Spectrum Frequency Modulation (DITH)
      9. 8.3.9  Configurable Soft Start (SS1, SS2)
      10. 8.3.10 Output Voltage Setpoint (FB1, FB2)
      11. 8.3.11 Minimum Controllable On-Time
      12. 8.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
      13. 8.3.13 Slope Compensation
      14. 8.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
        1. Shunt Current Sensing
        2. Inductor DCR Current Sensing
      15. 8.3.15 Hiccup Mode Current Limiting (RES)
      16. 8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
      17. 8.3.17 Output Configurations (MODE, FB2)
        1. Independent Dual-Output Operation
        2. Single-Output Interleaved Operation
        3. Single-Output Multiphase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Modes
      2. 8.4.2 Diode Emulation Mode
      3. 8.4.3 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. Buck Inductor
        2. Output Capacitors
        3. Input Capacitors
        4. Power MOSFETs
        5. EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency, Dual-Output Buck Regulator for Automotive Applications
        1. Design Requirements
        2. Detailed Design Procedure
          1. Custom Design With WEBENCH® Tools
          2. Custom Design With Excel Quickstart Tool
          3. Inductor Calculation
          4. Current-Sense Resistance
          5. Output Capacitors
          6. Input Capacitors
          7. Compensation Components
        3. Application Curves
      2. 9.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. Design Requirements
        2. Detailed Design Procedures
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate-Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. PCB Layout Resources
        2. Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Gate-Drive Layout

The LM5143-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

  • Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap (boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace. Refer to loop 2 of Figure 11-1.
  • Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. Refer to loop 3 of Figure 11-1.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.

  1. Connections from gate driver outputs, HO1/2, HOL1/2, LO1/2, and LOL1/2 to the respective gates of the high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as 4.25 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from the LM5143-Q1 to the high-side MOSFET, taking advantage of flux cancellation.
  2. Minimize the current loop path from the VCC and HB pins through their respective capacitors as these provide the high instantaneous current, up to 4.25 A, to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitor, CBST, close to the HB and SW pins of the LM5143-Q1 to minimize the area of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the LM5143-Q1 to minimize the area of loop 3 associated with the low-side driver.