SNVSAZ0C March   2018  – October 2021 LM51501-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUM|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.8 Loop Compensation Component Selection and Maximum ESR

Based on Equation 18, CCOMP is calculated using Equation 34 and Equation 35:

Equation 34. GUID-77F7C17F-1089-4DBD-A897-1A9E7D73E381-low.gif
Equation 35. GUID-D42573F9-E455-46AF-B61C-5B06019DC94A-low.gif

By selecting CCOMP following Equation 34, the typical phase margin is set to 90⁰ and the loop response is overdamped. In this example, FZ_EA is placed at a frequency 3 times higher than the FLP to have lower phase margin but faster settling time (K2 = 3, target FZ_EA is 860 Hz). The recommended range of FZ_EA is from 1 × FLP to 4 × FLP (1 ≤ K2 ≤ 4). Practical crossover frequency will vary with K2 with a range of 0.5 × FCROSS to 1.0 × FCROSS.

Equation 36. GUID-795DCFCA-02C0-4323-8B3E-477E7BCCFE9D-low.gif

A standard value of 56 nF is chosen for CCOMP.

RCOMP is selected to set the error amplifier zero at 860 Hz.

Equation 37. GUID-AC9025DB-C1B3-4901-8848-7E00AF1F54BE-low.gif

A standard value of 3.32 kΩ is chosen for RCOMP.

CHF is usually used to create a pole at high frequency (FP_EA) to cancel FZ_ESR. By using a small ESR capacitor that can place FZ_ESR greater than 10 × FCROSS, the output capacitor ESR would not affect the loop stability. The maximum ESR which does not affect the loop response is calculated using Equation 38.

Equation 38. GUID-0468E253-B6FD-404C-B93F-EE6EDD546731-low.gif