SNVSB75D December   2018  – January 2021 LM5155 , LM51551

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Clock Synchronization (UVLO/SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the UVLO/SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization clock must pull down the UVLO/SYNC pin voltage below 1.45 V (typical). The duty cycle of the pulldown pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup pulse width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown function. The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts down 35 µs (typical) after the UVLO pin is grounded.

GUID-FC4A83B3-6AA0-46E2-BA50-155A05D1FB46-low.gifFigure 9-10 UVLO and Shutdown

Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts down if the fSYNC stays in high logic state for longer than 35 µs (typical) (UVLO is in low logic state for more than 35 µs (typical)). The device runs at fSYNC if clock pulses are provided after the device is enabled.

GUID-4F77AD61-003F-42DB-B966-84169BA103ED-low.gifFigure 9-11 UVLO, Shutdown, and Clock Synchronization

Figure 9-13 and Figure 9-14 show implementations of standby and clock synchronization functions together. In this configuration, the device stops switching immediately if fSYNC stays in high logic state and enters standby mode if fSYNC stays in high logic state for longer than two switching cycles. The device runs at the fSYNC if clock pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable threshold for more than 1.5 µs, the configurations in Figure 9-13 and Figure 9-14 are recommended if the external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-12 shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is greater than 1.1 MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs before applying the external synchronization pulse.

GUID-B5621BBD-E19C-47E3-BA06-E24234EBF519-low.gifFigure 9-12 Required Duty Cycle to Start up by SYNC
GUID-DBB782BA-3054-41EF-908A-5AA13C4A7F05-low.gifFigure 9-13 UVLO, Standby, and Clock Synchronization (a)
GUID-E4FEF785-5EE9-403C-8DF3-54E65772C732-low.gifFigure 9-14 UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays in low logic state for longer than 35 µs (typical). The device is enabled if fSYNC stays in high logic state for longer than 1.5 µs. The device runs at the fSYNC if clock pulses are provided after the device is enabled. Also, in this configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be supplied before the BIAS is supplied (see Figure 9-15).

GUID-C242AD5E-62E5-4481-8CB8-D83CA6EEECE2-low.gifFigure 9-15 Shutdown and Clock Synchronization

Figure 9-16 shows an implementation of inverted enable using external circuit.

GUID-750B12B1-815D-4E37-844E-4350BA6DC26B-low.gifFigure 9-16 Inverted UVLO

The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Because the maximum duty cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization, take extra care when using the clock synchronization function. See Section 9.3.6, Section 9.3.7, and Section 9.3.11 for more information.