The feedback resistor divider is connected to an internal transconductance error amplifier which features high output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in Equation 14.
The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is 3.8 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be clamped with an external zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum COMP clamp is disabled when FB is connected to ground in flyback topology.