The device has a low-side current sense and provides both fixed and optional programmable slope compensation ramps, which help prevent subharmonic oscillation at high duty cycle. Both fixed and programmable slope compensation ramps are added to the sensed inductor current input for the PWM operation, but only the programmable slope compensation ramp is added to the sensed inductor current input (see Figure 9-18). For an accurate peak current limit operation over the input supply voltage, TI recommends using only the fixed slope compensation (see Figure 8-5).
The device can generate the programmable slope compensation ramp using an external slope resistor (RSL) and a sawtooth current source with a slope of 30 μA × fRT. This current flows out of the CS pin.
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation in boost topology should satisfy the following inequality:
The recommended margin to cover non-ideal factors is 1.2. If required, RSL can be added to further increase the slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope compensation. The RSL value to achieve 82% of the sensed inductor current falling slope is calculated as shown in Equation 9.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used, the fSW frequency equals the fSYNC frequency. The maximum value for the RSL resistance is 2 kΩ.