The device senses switch current which flows into the SW pin, and provides a fixed internal slope compensation ramp, helping prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is added to the sensed switch current for the PWM operation, but no slope compensation ramp is added to the sensed inductor current for the current limit operation to provide an accurate peak current limit over the input supply voltage (see Figure 9-17).
Use Equation 6 to calculate the value of the peak slope voltage (VSLOPE).
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation in boost topology must satisfy the following inequality:
Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used, the fSW frequency equals the fSYNC frequency.